公开(公告)号：US12295140B2

公开(公告)日：2025-05-06

申请号：US17533580

申请日：2021-11-23

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Allen McTeer ,  Rita J. Klein ,  John D. Hopkins ,  Nancy M. Lomeli ,  Xiao Li ,  Alyssa N. Scarbrough ,  Jiewei Chen ,  Naiming Liu ,  Shuangqiang Luo ,  Silvia Borsari ,  John Mark Meldrim ,  Shen Hu

IPC: H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks. A through-array-via (TAV) region comprises TAV constructions that extend through the insulative tiers and the conductive tiers. The TAV constructions individually comprise a radially-outer insulative lining and a conductive core radially-inward of the insulative lining. The insulative lining comprises a radially-inner insulative material and a radially-outer insulative material that are of different compositions relative one another. The radially-outer insulative material is in radially-outer recesses that are in the first tiers as compared to the second tiers. The radially-inner insulative material extends elevationally along the insulative tiers and the conductive tiers. Other embodiments, including method, are disclosed.

公开(公告)号：US20170141119A1

公开(公告)日：2017-05-18

申请号：US14942823

申请日：2015-11-16

Applicant: Micron Technology, Inc.

Inventor： Yongjun Jeff Hu ,  Allen McTeer

IPC: H01L27/115 ,  H01L21/322 ,  H01L21/02

CPC classification number: H01L27/11524 ,  H01L21/02672 ,  H01L21/3221 ,  H01L27/1157 ,  H01L27/11582

Abstract: Some embodiments include an integrated structure having semiconductor material within a region between two parallel surfaces. The semiconductor material has grain boundaries parallel to the parallel surfaces. At least one circuit component utilizes a region of the semiconductor material in a gated device. The semiconductor material has little if any metal therein so that the gated device has Ion/Ioff characteristics similar to if the semiconductor material had no metal therein. Some embodiments include a method in which semiconductor material is provided between a pair of parallel surfaces, and in which the parallel surfaces and semiconductor material extend between a first end and a second end. Metal is formed adjacent the first end, and gettering material is formed adjacent the second end. Thermal processing induces crystallization of the semiconductor material and drives the metal along the semiconductor material and into the gettering material. The gettering material is then removed.

公开(公告)号：US20160211324A1

公开(公告)日：2016-07-21

申请号：US14597766

申请日：2015-01-15

Applicant: Micron Technology, Inc.

Inventor： Shu Qin ,  Yongjun Jeff Hu ,  Allen McTeer

IPC: H01L29/08 ,  H01L21/223 ,  H01L27/092 ,  H01L29/45

CPC classification number: H01L29/0847 ,  H01L21/2236 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/823418 ,  H01L27/092 ,  H01L29/456 ,  H01L29/665

Abstract: Some embodiments include a device having an n-type diffusion region, and having a boron-doped region within the n-type diffusion region. The boron-doped region extends no deeper than about 10 nanometers from an upper surface of the n-type diffusion region. Some embodiments include a method in which first boron-enhanced regions are formed within upper portions of n-type source/drain regions of an NMOS (n-type metal-oxide-semiconductor) device and second boron-enhanced regions are simultaneously formed within upper portions of p-type source/drain regions of a PMOS (p-type metal-oxide-semiconductor) device. The first and second boron-enhanced regions extend to depths of less than or equal to about 10 nanometers.

Abstract translation: 一些实施例包括具有n型扩散区的器件，并且在n型扩散区内具有硼掺杂区。 硼掺杂区从n型扩散区的上表面延伸不超过约10纳米。 一些实施例包括其中在NMOS（n型金属氧化物 - 半导体）器件的n型源极/漏极区的上部形成第一硼增强区的方法，并且第二硼增强区同时形成在上部 PMOS（p型金属氧化物半导体）器件的p型源/漏区的部分。 第一和第二硼增强区域延伸到小于或等于约10纳米的深度。

公开(公告)号：US20150357334A1

公开(公告)日：2015-12-10

申请号：US14829818

申请日：2015-08-19

Applicant: Micron Technology, Inc.

Inventor： Yongjun Jeff Hu ,  Allen McTeer

IPC: H01L27/108 ,  H01L23/528 ,  H01L29/167 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L27/10805 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2656 ,  H01L23/528 ,  H01L27/088 ,  H01L27/10873 ,  H01L27/10882 ,  H01L29/167 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An array includes vertically-oriented transistors, rows of access lines, and columns of data/sense lines. Individual of the rows include an access line interconnecting transistors in that row. Individual of the columns include a data/sense line interconnecting transistors in that column. The data/sense line has silicon-comprising semiconductor material between the transistors in that column that is conductively-doped n-type with at least one of As and Sb. The conductively-doped semiconductor material of the data/sense line includes a conductivity-neutral dopant between the transistors in that column. Methods are disclosed.

Abstract translation: 阵列包括垂直取向的晶体管，访问线的行和数据/感测线的列。 这些行的单独包括在该行中互连晶体管的访问线。 列的单独包括在该列中互连晶体管的数据/感测线。 数据/检测线在该列中的晶体管之间具有含硅的半导体材料，该导体掺杂n型与As和Sb中的至少一种导电掺杂。 数据/检测线的导电掺杂半导体材料包括该列中的晶体管之间的导电中性掺杂剂。 公开了方法。

公开(公告)号：US09786475B2

公开(公告)日：2017-10-10

申请号：US14218428

申请日：2014-03-18

Applicant: Micron Technology, Inc.

Inventor： Shu Qin ,  Allen McTeer

IPC: H01J37/32 ,  G01N21/73 ,  C23C14/54 ,  C23C16/52

CPC classification number: H01J37/32917 ,  C23C14/54 ,  C23C16/52 ,  G01N21/73 ,  H01J37/32935 ,  H01J37/32972

Abstract: Systems and methods for plasma processing of microfeature workpieces are disclosed herein. In one embodiment, a method includes generating a plasma in a chamber while a microfeature workpiece is positioned in the chamber, measuring optical emissions from the plasma, and determining a parameter of the plasma based on the measured optical emissions. The parameter can be an ion density or another parameter of the plasma.

公开(公告)号：US09780103B2

公开(公告)日：2017-10-03

申请号：US14942823

申请日：2015-11-16

Applicant: Micron Technology, Inc.

Inventor： Yongjun Jeff Hu ,  Allen McTeer

IPC: H01L27/115 ,  H01L27/11524 ,  H01L21/02 ,  H01L21/322 ,  H01L27/1157

CPC classification number: H01L27/11524 ,  H01L21/02672 ,  H01L21/3221 ,  H01L27/1157 ,  H01L27/11582

Abstract: Some embodiments include an integrated structure having semiconductor material within a region between two parallel surfaces. The semiconductor material has grain boundaries parallel to the parallel surfaces. At least one circuit component utilizes a region of the semiconductor material in a gated device. The semiconductor material has little if any metal therein so that the gated device has Ion/Ioff characteristics similar to if the semiconductor material had no metal therein. Some embodiments include a method in which semiconductor material is provided between a pair of parallel surfaces, and in which the parallel surfaces and semiconductor material extend between a first end and a second end. Metal is formed adjacent the first end, and gettering material is formed adjacent the second end. Thermal processing induces crystallization of the semiconductor material and drives the metal along the semiconductor material and into the gettering material. The gettering material is then removed.

公开(公告)号：US09472663B2

公开(公告)日：2016-10-18

申请号：US14679703

申请日：2015-04-06

Applicant: Micron Technology, Inc.

Inventor： Yongjun Jeff Hu ,  Allen McTeer

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/161 ,  H01L29/167 ,  H01L21/265 ,  H01L29/36 ,  H01L27/108

CPC classification number: H01L29/7827 ,  H01L21/26506 ,  H01L21/26513 ,  H01L27/108 ,  H01L27/10873 ,  H01L27/10882 ,  H01L29/161 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66666

Abstract: An n-type field effect transistor includes silicon-comprising semiconductor material comprising a pair of source/drain regions having a channel region there-between. At least one of the source/drain regions is conductively doped n-type with at least one of As and P. A conductivity-neutral dopant is in the silicon-comprising semiconductor material in at least one of the channel region and the at least one source/drain region. A gate construction is operatively proximate the channel region. Methods are disclosed.

公开(公告)号：US20130288466A1

公开(公告)日：2013-10-31

申请号：US13929590

申请日：2013-06-27

Applicant: Micron Technology, Inc.

Inventor： Lequn Jennifer Liu ,  Shu Qin ,  Allen McTeer ,  Yongjun Jeff Hu

IPC: H01L21/223

CPC classification number: H01L21/2236 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/26526 ,  H01L29/66575

Abstract: Some embodiments include methods of forming one or more doped regions in a semiconductor substrate. Plasma doping may be used to form a first dopant to a first depth within the substrate. The first dopant may then be impacted with a second dopant to knock the first dopant to a second depth within the substrate. In some embodiments the first dopant is p-type (such as boron) and the second dopant is neutral type (such as germanium). In some embodiments the second dopant is heavier than the first dopant.

公开(公告)号：US20190267390A1

公开(公告)日：2019-08-29

申请号：US16406504

申请日：2019-05-08

Applicant: Micron Technology, Inc.

Inventor： Yongjun Jeff Hu ,  Allen McTeer

IPC: H01L27/11524 ,  H01L27/11582 ,  H01L21/322 ,  H01L21/02 ,  H01L27/1157

Abstract: Some embodiments include an integrated structure having semiconductor material within a region between two parallel surfaces. The semiconductor material has grain boundaries parallel to the parallel surfaces. At least one circuit component utilizes a region of the semiconductor material in a gated device. The semiconductor material has little if any metal therein so that the gated device has Ion/Ioff characteristics similar to if the semiconductor material had no metal therein. Some embodiments include a method in which semiconductor material is provided between a pair of parallel surfaces, and in which the parallel surfaces and semiconductor material extend between a first end and a second end. Metal is formed adjacent the first end, and gettering material is formed adjacent the second end. Thermal processing induces crystallization of the semiconductor material and drives the metal along the semiconductor material and into the gettering material. The gettering material is then removed.

公开(公告)号：US20170373076A1

公开(公告)日：2017-12-28

申请号：US15686107

申请日：2017-08-24

Applicant: Micron Technology, Inc.

Inventor： Yongjun Jeff Hu ,  Allen McTeer

IPC: H01L27/11524 ,  H01L21/02 ,  H01L21/322 ,  H01L27/1157

CPC classification number: H01L27/11524 ,  H01L21/02672 ,  H01L21/3221 ,  H01L27/1157 ,  H01L27/11582

Abstract: Some embodiments include an integrated structure having semiconductor material within a region between two parallel surfaces. The semiconductor material has grain boundaries parallel to the parallel surfaces. At least one circuit component utilizes a region of the semiconductor material in a gated device. The semiconductor material has little if any metal therein so that the gated device has Ion/Ioff characteristics similar to if the semiconductor material had no metal therein. Some embodiments include a method in which semiconductor material is provided between a pair of parallel surfaces, and in which the parallel surfaces and semiconductor material extend between a first end and a second end. Metal is formed adjacent the first end, and gettering material is formed adjacent the second end. Thermal processing induces crystallization of the semiconductor material and drives the metal along the semiconductor material and into the gettering material. The gettering material is then removed.