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1.发明公开公开(公告)号：US20240079057A1
公开(公告)日：2024-03-07
申请号：US17930279
申请日：2022-09-07
IPC分类号： G11C16/04 , H01L27/11519 , H01L27/11524 , H01L27/11551 , H01L27/11565 , H01L27/1157 , H01L27/11578
CPC分类号： G11C16/0483 , H01L27/11519 , H01L27/11524 , H01L27/11551 , H01L27/11565 , H01L27/1157 , H01L27/11578
摘要： A microelectronic device comprises a stack structure overlying a source tier. The stack structure comprises a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The microelectronic device comprises a staircase structure within the stack structure and having steps comprising lateral edges of the tiers, conductive contacts within a horizontal area of the staircase structure and vertically extending through the stack structure to the source tier, and strapping structures laterally adjacent to the conductive contacts and having upper surfaces substantially coplanar with upper surfaces of the conductive contacts. Each of the strapping structures are in contact with one of the conductive contacts and with one of the conductive structures of the stack structure at one of the steps of the staircase structure. Related memory devices, electronic systems, and methods of forming the microelectronic devices are also described.
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公开(公告)号：US11837267B2
公开(公告)日：2023-12-05
申请号：US17325997
申请日：2021-05-20
CPC分类号： G11C11/1673 , G11C11/1659 , G11C11/1675
摘要： Methods, systems, devices, and other implementations to store fuse data in memory devices are described. Some implementations may include an array of memory cells with different portions of cells for storing data. A first portion of the array may store fuse data and may contain a chalcogenide storage element, while a second portion of the array may store user data. Sense circuitry may be coupled with the array, and may determine the value of the fuse data using various signaling techniques. In some cases, the sense circuitry may implement differential storage and differential signaling to determine the value of the fuse data stored in the first portion of the array.
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公开(公告)号：US11417398B2
公开(公告)日：2022-08-16
申请号：US17108783
申请日：2020-12-01
摘要： Methods, systems, and devices for memory cells for storing operational data are described. A memory device may include an array of memory cells with different sets of cells for storing data. A first set of memory cells may store data for operating the memory device, and the associated memory cells may each contain a chalcogenide storage element. A second set of memory cells may store host data. Some memory cells included in the first set may be programmed to store a first logic state and other memory cells in the first set may be left unprogrammed (and may represent a second logic state). Sense circuitry may be coupled with the array and may determine a value of data stored by the first set of memory cells.
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公开(公告)号：US11037613B2
公开(公告)日：2021-06-15
申请号：US16514431
申请日：2019-07-17
摘要： Methods, systems, devices, and other implementations to store fuse data in memory devices are described. Some implementations may include an array of memory cells with different portions of cells for storing data. A first portion of the array may store fuse data and may contain a chalcogenide storage element, while a second portion of the array may store user data. Sense circuitry may be coupled with the array, and may determine the value of the fuse data using various signaling techniques. In some cases, the sense circuitry may implement differential storage and differential signaling to determine the value of the fuse data stored in the first portion of the array.
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公开(公告)号：US11018300B2
公开(公告)日：2021-05-25
申请号：US16665955
申请日：2019-10-28
发明人： Agostino Pirovano , Fabio Pellizzer , Anna Maria Conti , Andrea Redaelli , Innocenzo Tortorelli
摘要： A multi-layer memory device with an array having multiple memory decks of self-selecting memory cells is provided in which N memory decks may be fabricated with N+1 mask operations. The multiple memory decks may be self-aligned and certain manufacturing operations may be performed for multiple memory decks at the same time. For example, patterning a bit line direction of a first memory deck and a word line direction in a second memory deck above the first memory deck may be performed in a single masking operation, and both decks may be etched in a same subsequent etching operation. Such techniques may provide efficient fabrication which may allow for enhanced throughput, additional capacity, and higher yield for fabrication facilities relative to processing techniques in which each memory deck is processed using two or more mask and etch operations per memory deck.
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公开(公告)号：US20210043685A1
公开(公告)日：2021-02-11
申请号：US16534952
申请日：2019-08-07
发明人： Andrea Redaelli , Anna Maria Conti
IPC分类号： H01L27/24 , H01L21/3213 , H01L21/768 , H01L45/00 , H01L27/11514 , H01L23/528
摘要： Methods, systems, and devices for access line formation for a memory array are described. The techniques described herein may be used to fabricate access lines for one or more decks of a memory array. In some examples, one or more access lines of a deck may be formed using an independent processing step. For example, different fabrication processes may be used to form a plurality of access lines in a deck and to form the pillars (e.g., the memory cells) that are coupled with the access lines. In some examples, an offset between the access lines and the pillars may exist due to the components being fabricated in different processing steps.
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公开(公告)号：US20210020218A1
公开(公告)日：2021-01-21
申请号：US16514431
申请日：2019-07-17
IPC分类号： G11C11/16
摘要： Methods, systems, devices, and other implementations to store fuse data in memory devices are described. Some implementations may include an array of memory cells with different portions of cells for storing data. A first portion of the array may store fuse data and may contain a chalcogenide storage element, while a second portion of the array may store user data. Sense circuitry may be coupled with the array, and may determine the value of the fuse data using various signaling techniques. In some cases, the sense circuitry may implement differential storage and differential signaling to determine the value of the fuse data stored in the first portion of the array.
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公开(公告)号：US10693065B2
公开(公告)日：2020-06-23
申请号：US15893100
申请日：2018-02-09
摘要： Methods, systems, and devices for a tapered cell profile and fabrication are described. A memory storage component may contain multiple chalcogenide materials and may include a tapered profile. For example, a first chalcogenide material may be coupled with a second chalcogenide material. Each of the chalcogenide materials may be further coupled with a conductive material (e.g., an electrode). Through an etching process, the chalcogenide materials may tapered (e.g., step tapered). A pulse may be applied to the tapered chalcogenide materials resulting in a memory storage component that includes a mixture of the chalcogenide materials.
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公开(公告)号：US20190252605A1
公开(公告)日：2019-08-15
申请号：US15893100
申请日：2018-02-09
摘要： Methods, systems, and devices for a tapered cell profile and fabrication are described. A memory storage component may contain multiple chalcogenide materials and may include a tapered profile. For example, a first chalcogenide material may be coupled with a second chalcogenide material. Each of the chalcogenide materials may be further coupled with a conductive material (e.g., an electrode). Through an etching process, the chalcogenide materials may tapered (e.g., step tapered). A pulse may be applied to the tapered chalcogenide materials resulting in a memory storage component that includes a mixture of the chalcogenide materials.
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公开(公告)号：US20190088534A1
公开(公告)日：2019-03-21
申请号：US16183493
申请日：2018-11-07
发明人： Marcello Mariani , Anna Maria Conti , Sara Vigano
IPC分类号： H01L21/762 , H01L21/308 , H01L29/749 , H01L29/744 , H01L21/8249 , H01L21/8239 , H01L29/66 , H01L27/102 , H01L27/105 , H01L21/8234 , H01L29/423 , H01L21/8229 , H01L29/78
CPC分类号： H01L21/76224 , H01L21/308 , H01L21/8229 , H01L21/823437 , H01L21/823475 , H01L21/823487 , H01L21/8239 , H01L21/8249 , H01L27/1022 , H01L27/1027 , H01L27/1052 , H01L29/4236 , H01L29/42364 , H01L29/66333 , H01L29/66363 , H01L29/66666 , H01L29/744 , H01L29/749 , H01L29/7827
摘要： An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed.
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