公开(公告)号：US20130302981A1

公开(公告)日：2013-11-14

申请号：US13941747

申请日：2013-07-15

Applicant: Micron Technology, Inc.

Inventor： Dan Millward ,  Kaveri Jain ,  Zishu Zhang ,  Lijing Gou ,  Anton J. deVilliers ,  Jianming Zhou ,  Yuan He ,  Michael D. Hyatt ,  Scott L. Light

IPC: H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10882 ,  H01L27/10888

Abstract: Some embodiments include methods of forming patterns. A semiconductor substrate is formed to comprise an electrically insulative material over a set of electrically conductive structures. An interconnect region is defined across the electrically conductive structures, and regions on opposing sides of the interconnect region are defined as secondary regions. A two-dimensional array of features is formed over the electrically insulative material. The two-dimensional array extends across the interconnect region and across the secondary regions. A pattern of the two-dimensional array is transferred through the electrically insulative material of the interconnect region to form contact openings that extend through the electrically insulative material and to the electrically conductive structures, and no portions of the two-dimensional array of the secondary regions is transferred into the electrically insulative material.

Abstract translation: 一些实施例包括形成图案的方法。 半导体衬底被形成为在一组导电结构之上包括电绝缘材料。 跨导电结构限定互连区域，并且互连区域的相对侧上的区域被定义为次级区域。 特征的二维阵列形成在电绝缘材料上。 二维阵列跨越互连区域并跨越次级区域延伸。 二维阵列的图案通过互连区域的电绝缘材料转移以形成延伸穿过电绝缘材料和导电结构的接触开口，并且二次区域的二维阵列的任何部分 被转移到电绝缘材料中。

公开(公告)号：US20130252142A1

公开(公告)日：2013-09-26

申请号：US13892711

申请日：2013-05-13

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Kaveri Jain ,  Lijing Gou ,  Zishu Zhang ,  Anton J. deVilliers ,  Michael Hyatt ,  Jianming Zhou ,  Scott L. Light ,  Dan B. Millward

IPC: G03F1/38

CPC classification number: G03F1/38 ,  G03F1/50 ,  G03F1/54 ,  Y10T29/49002

Abstract: An imaging device comprising a first region and a second region. Imaging features in the first region and assist features in the second region are substantially the same size as one another and are formed substantially on pitch. Methods of forming an imaging device and methods of forming a semiconductor device structure are also disclosed.

Abstract translation: 一种成像装置，包括第一区域和第二区域。 第一区域中的成像特征和第二区域中的辅助特征基本上彼此相同，并且基本上在间距上形成。 还公开了形成成像装置的方法和形成半导体器件结构的方法。

公开(公告)号：US10461038B1

公开(公告)日：2019-10-29

申请号：US16118902

申请日：2018-08-31

Applicant: Micron Technology, Inc.

Inventor： Richard T. Housley ,  Jianming Zhou

IPC: H01L21/00 ,  H01L23/544 ,  H01L21/78

Abstract: Some embodiments include a semiconductor package. The semiconductor package has a semiconductor die with a primary region which includes integrated circuitry, and with an edge region which includes a portion of an alignment mark location. The portion of the alignment mark location includes a segment of an alignment mark. The alignment mark includes a pattern of lines and spaces, with the lines extending along a first direction. The portion of the alignment mark location also includes a texture having a pattern other than lines extending along either the first direction or along a second direction substantially orthogonal to the first direction. Some embodiments include methods for alignment marking semiconductor wafers.

公开(公告)号：US09460998B2

公开(公告)日：2016-10-04

申请号：US14259313

申请日：2014-04-23

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Ranjan Khurana ,  David Swindler ,  Jianming Zhou

IPC: H01L23/52 ,  H01L23/528 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include a semiconductor construction having a pair of lines extending primarily along a first direction, and having a pair of contacts between the lines. The contacts are spaced from one another by a lithographic dimension, and are spaced from the lines by sub-lithographic dimensions. Some embodiments include a method of forming a semiconductor construction. Features are formed over a base. Each feature has a first type sidewall and a second type sidewall. The features are spaced from one another by gaps. Some of the gaps are first type gaps between first type sidewalls, and others of the gaps are second type gaps between second type sidewalls. Masking material is formed to selectively fill the first type gaps relative to the second type gaps. Excess masking material is removed to leave a patterned mask. A pattern is transferred from the patterned mask into the base.

Abstract translation: 一些实施例包括具有主要沿着第一方向延伸的一对线并且在线之间具有一对接触的半导体结构。 触点通过光刻尺寸彼此间隔开，并且通过亚光刻尺寸与线间隔开。 一些实施例包括形成半导体结构的方法。 特征形成在一个基地上。 每个特征具有第一类型侧壁和第二类型侧壁。 这些特征通过间隙彼此间隔开。 一些间隙是第一类型侧壁之间的第一类型间隙，而其它间隙是第二类型侧壁之间的第二类型间隙。 形成掩模材料以相对于第二类型间隙选择性地填充第一类型的间隙。 去除过量的掩模材料以留下图案化掩模。 图案从图案化掩模转移到基底中。

公开(公告)号：US20140106280A1

公开(公告)日：2014-04-17

申请号：US14107767

申请日：2013-12-16

Applicant: Micron Technology, Inc.

Inventor： Jianming Zhou ,  Scott L. Light ,  David Kewley ,  Prasanna Srinivasan ,  Anton deVilliers

IPC: G03F7/20

CPC classification number: G03F7/20 ,  G03F1/26 ,  G03F1/32 ,  G03F7/70433 ,  G03F7/70883

Abstract: Methods of lithography, methods for forming patterning tools, and patterning tools are described. One such patterning tool include an active region that forms a first diffraction image on a lens when in use, and an inactive region that forms a second diffraction image on a lens when in use. The inactive region includes a pattern of phase shifting features formed in a substantially transparent material of the patterning tool. Patterning tools and methods, as described, can be used to compensate for lens distortion from effects such as localized heating.

Abstract translation: 描述了光刻方法，用于形成图案形成工具的方法和图案形成工具。 一种这样的图案形成工具包括在使用时在透镜上形成第一衍射图像的有源区域和在使用时在透镜上形成第二衍射图像的非活性区域。 非活性区域包括形成在图案形成工具的基本上透明的材料中的相移特征的图案。 如所描述的图案化工具和方法可用于补偿透镜失真，例如局部加热等影响。

公开(公告)号：US11075169B2

公开(公告)日：2021-07-27

申请号：US16226074

申请日：2018-12-19

Applicant: Micron Technology, Inc.

Inventor： Denzil S. Frost ,  Richard T. Housley ,  Jianming Zhou

IPC: H01L23/544

Abstract: A method of forming an overlay alignment mark in the fabrication of integrated circuitry comprises forming a first series of periodically-horizontally-spaced lower first features on a substrate. A second series of periodically-horizontally-spaced upper second features is formed directly above the first series of the lower first features. Individual of the upper second features are directly above and cover at least a portion of individual of the lower first features in a first horizontal area of the substrate. Individual of the upper second features are not directly above and are not covering any portion of the individual lower first features in a second horizontal area of the substrate that is horizontally adjacent the first horizontal area. Other methods, and structure independent of method, are disclosed.

公开(公告)号：US20200075500A1

公开(公告)日：2020-03-05

申请号：US16554118

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： Richard T. Housley ,  Jianming Zhou

IPC: H01L23/544 ,  H01L21/78

Abstract: Some embodiments include a semiconductor package. The semiconductor package has a semiconductor die with a primary region which includes integrated circuitry, and with an edge region which includes a portion of an alignment mark location. The portion of the alignment mark location includes a segment of an alignment mark. The alignment mark includes a pattern of lines and spaces, with the lines extending along a first direction. The portion of the alignment mark location also includes a texture having a pattern other than lines extending along either the first direction or along a second direction substantially orthogonal to the first direction. Some embodiments include methods for alignment marking semiconductor wafers.

公开(公告)号：US20150015860A1

公开(公告)日：2015-01-15

申请号：US14500625

申请日：2014-09-29

Applicant: Micron Technology, Inc.

Inventor： Scott L. Light ,  Dan Millward ,  Yuan He ,  Kaveri Jain ,  Lijing Gou ,  Zishu Zhang ,  Anton J. deVilliers ,  Michael D. Hyatt ,  Jianming Zhou

IPC: G03F7/20

CPC classification number: G03F7/70741 ,  G03F1/38 ,  G03F7/70433 ,  G03F7/70891

Abstract: A method of mitigating asymmetric lens heating in photolithographically patterning a photo-imageable material using a reticle includes determining where first hot spot locations are expected to occur on a lens when using a reticle to pattern a photo-imageable material. The reticle is then fabricated to include non-printing features within a non-printing region of the reticle which generate additional hot spot locations on the lens when using the reticle to pattern the photo-imageable material. Other implementations are contemplated, including reticles which may be independent of method of use or fabrication.

Abstract translation: 使用光掩模光刻地图案化可光成像材料的方法来减轻不对称透镜加热的方法包括当使用掩模版图案可光成像材料时，确定预期在透镜上将出现第一热点位置的位置。 然后制造掩模版以在掩模版的非印刷区域内包括非印刷特征，当使用掩模版对可光成像材料进行图案化时，其在透镜上产生额外的热点位置。 考虑了其他实施方式，包括可以独立于使用或制造方法的标线。

公开(公告)号：US10756022B2

公开(公告)日：2020-08-25

申请号：US16554118

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： Richard T. Housley ,  Jianming Zhou

IPC: H01L21/00 ,  H01L23/544 ,  H01L21/78

Abstract: Some embodiments include a semiconductor package. The semiconductor package has a semiconductor die with a primary region which includes integrated circuitry, and with an edge region which includes a portion of an alignment mark location. The portion of the alignment mark location includes a segment of an alignment mark. The alignment mark includes a pattern of lines and spaces, with the lines extending along a first direction. The portion of the alignment mark location also includes a texture having a pattern other than lines extending along either the first direction or along a second direction substantially orthogonal to the first direction. Some embodiments include methods for alignment marking semiconductor wafers.

公开(公告)号：US09176385B2

公开(公告)日：2015-11-03

申请号：US14107767

申请日：2013-12-16

Applicant: Micron Technology, Inc.

Inventor： Jianming Zhou ,  Scott L. Light ,  David Kewley ,  Prasanna Srinivasan ,  Anton deVilliers

IPC: G03F1/44 ,  G03F7/20 ,  G03F1/26 ,  G03F1/32

CPC classification number: G03F7/20 ,  G03F1/26 ,  G03F1/32 ,  G03F7/70433 ,  G03F7/70883

Abstract: Methods of lithography, methods for forming patterning tools, and patterning tools are described. One such patterning tool include an active region that forms a first diffraction image on a lens when in use, and an inactive region that forms a second diffraction image on a lens when in use. The inactive region includes a pattern of phase shifting features formed in a substantially transparent material of the patterning tool. Patterning tools and methods, as described, can be used to compensate for lens distortion from effects such as localized heating.

Abstract translation: 描述了光刻方法，用于形成图案形成工具的方法和图案形成工具。 一种这样的图案形成工具包括在使用时在透镜上形成第一衍射图像的有源区域和在使用时在透镜上形成第二衍射图像的非活性区域。 非活性区域包括形成在图案形成工具的基本上透明的材料中的相移特征的图案。 如所描述的图案化工具和方法可用于补偿透镜失真，例如局部加热等影响。