中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

25 records (took 0.015 seconds)

    Memory sub-system self-testing operations
    1.
    发明授权
    Memory sub-system self-testing operations 有权

    公开(公告)号：US11514995B2

    公开(公告)日：2022-11-29

    申请号：US17211133

    申请日：2021-03-24

    Applicant: Micron Technology, Inc.

    Inventor： Nathan A. Eckel ,  Keith A. Benjamin

    IPC: G11C29/12 ,  G11C29/02 ,  G11C29/38 ,  G11C29/50 ,  G11C29/48

    Abstract: A method includes requesting, by a component of a memory sub-system controller, control of a data path associated with a memory device coupleable to the controller. The method can include generating, by the component, data corresponding to an operation to test the memory device and causing, by the component, the data to be injected to the data path such that the data is written to the memory device. The method can further include reading, by the component, the data written to the memory device and determining, by the component, whether the data read by the component from the memory device matches the data written to the memory device.

    PARTIAL SAVE OF MEMORY
    2.
    发明申请
    PARTIAL SAVE OF MEMORY 有权

    公开(公告)号：US20210019073A1

    公开(公告)日：2021-01-21

    申请号：US17065226

    申请日：2020-10-07

    Applicant: Micron Technology, Inc.

    Inventor： Jeffery J. Leyda ,  Nathan A. Eckel

    IPC: G06F3/06 ,  G06F12/0804

    Abstract: A variety of applications can include systems and/or methods of partial save of memory in an apparatus such as a non-volatile dual in-line memory module. In various embodiments, a set of control registers of a non-volatile dual in-line memory module can be configured to contain an identification of a portion of dynamic random-access memory of the non-volatile dual in-line memory module from which to back up content to non-volatile memory of the non-volatile dual in-line memory module. Registers of the set of control registers may also be allotted to contain an amount of content to transfer from the dynamic random-access memory content to the non-volatile memory. Additional apparatus, systems, and methods are disclosed.

    Partial save of memory
    3.
    发明授权
    Partial save of memory 有权

    公开(公告)号：US10831393B2

    公开(公告)日：2020-11-10

    申请号：US16113221

    申请日：2018-08-27

    Applicant: Micron Technology, Inc.

    Inventor： Jeffery J. Leyda ,  Nathan A. Eckel

    IPC: G06F12/00 ,  G06F3/06 ,  G06F12/0804

    Abstract: A variety of applications can include systems and/or methods of partial save of memory in an apparatus such as a non-volatile dual in-line memory module. In various embodiments, a set of control registers of a non-volatile dual in-line memory module can be configured to contain an identification of a portion of dynamic random-access memory of the non-volatile dual in-line memory module from which to back up content to non-volatile memory of the non-volatile dual in-line memory module. Registers of the set of control registers may also be allotted to contain an amount of content to transfer from the dynamic random-access memory content to the non-volatile memory. Additional apparatus, systems, and methods are disclosed.

    Apparatuses and methods for providing strobe signals to memories
    4.
    发明授权
    Apparatuses and methods for providing strobe signals to memories 有权

    公开(公告)号：US09437263B2

    公开(公告)日：2016-09-06

    申请号：US14871723

    申请日：2015-09-30

    Applicant: Micron Technology, Inc.

    Inventor： Nathan A. Eckel

    IPC: G11C7/00 ,  G11C7/22

    CPC classification number: G11C7/22 ,  G06F13/1689 ,  G11C7/222

    Abstract: Apparatuses and methods for providing strobe signals to memories are described herein. An example apparatus may include a plurality of memories and a memory controller. The memory controller may be coupled to the plurality of memories and configured to receive an input clock signal. The memory controller may further be configured to provide a timing strobe signal having a delay relative to the input clock signal to a memory of the plurality of memories. The memory controller may further be configured to receive a return strobe signal from the plurality of memories. In some examples, the return strobe signal may be based at least in part on the timing strobe signal and the memory controller may be configured to adjust the delay based, at least in part, on a phase difference of the input clock signal and the return strobe signal.

    INTERFACE LAYOUT FOR STACKED MEMORY ARCHITECTURES
    6.
    发明申请
    INTERFACE LAYOUT FOR STACKED MEMORY ARCHITECTURES 有权

    公开(公告)号：US20240402909A1

    公开(公告)日：2024-12-05

    申请号：US18670074

    申请日：2024-05-21

    Applicant: Micron Technology, Inc.

    Inventor： Nathan A. Eckel ,  Lance P. Johnson ,  Paul A. Laberge

    IPC: G06F3/06

    Abstract: Methods, systems, and devices for an interface layout for stacked memory architectures are described. A memory interface block may interface a plurality of memory dies to a host controller. The memory interface block may include an interface block coupled with multiple memory dies, which may be stacked on the memory interface block using through-silicon-vias. The memory interface block may include controllers, datapath blocks, and interface blocks associated with each memory die. As such, the memory interface block may perform functions such as queueing, ECC, and performing row repair and column repair procedures. In some examples, a layout for the memory interface block may include pairing controllers for at least two memory devices, such that a pair of controllers may share a command port to a pair of memory dies. Further, the memory interface block may include interfaces to the host controller that are different from the interface to each memory die.

    BOOT AND INITIALIZATION TECHNIQUES FOR STACKED MEMORY ARCHITECTURES
    8.
    发明申请
    BOOT AND INITIALIZATION TECHNIQUES FOR STACKED MEMORY ARCHITECTURES 有权

    公开(公告)号：US20240402925A1

    公开(公告)日：2024-12-05

    申请号：US18671485

    申请日：2024-05-22

    Applicant: Micron Technology, Inc.

    Inventor： Nathan A. Eckel

    IPC: G06F3/06

    Abstract: Methods, systems, and devices for boot and initialization techniques for stacked memory architectures are described. A memory system may include a common logic block operable to output an indication to each of a set of multiple interface blocks to initiate an initialization program, an evaluation program, or both, where the interface blocks may each be operable to access memory arrays via a respective set of one or more channels. The common logic block may receive a command to initialize or evaluate operations associated with the interface blocks or the respective memory arrays. The common logic block may output an indication of a set of instructions associated with the initialization or evaluation. The interface blocks may, using the received indication, obtain the instructions and perform one or more operations associated with the instructions. In some examples, the common logic block may output the indication in response to identifying a power-on condition.

    Storage backed memory package save trigger
    9.
    发明授权
    Storage backed memory package save trigger 有权

    公开(公告)号：US11074131B2

    公开(公告)日：2021-07-27

    申请号：US16847008

    申请日：2020-04-13

    Applicant: Micron Technology, Inc.

    Inventor： James E. Dunn ,  Nathan A. Eckel

    IPC: G06F11/14 ,  G06F13/42 ,  G11C14/00 ,  G11C5/14 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/406

    Abstract: Devices and techniques for a storage backed memory package save trigger are disclosed herein. Data can be received via a first interface. The data is stored in a volatile portion of the memory package. Here, the memory package includes a second interface arranged to connect a host to a controller in the memory package. A reset signal can be received at the memory package via the first interface. The data stored in the volatile portion of the memory package can be saved to a non-volatile portion of the memory package in response to the reset signal.

Patent Agency Ranking