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    DIE CORNER PROTECTION BY USING POLYMER DEPOSITION TECHNOLOGY
    1.
    发明申请
    DIE CORNER PROTECTION BY USING POLYMER DEPOSITION TECHNOLOGY 有权

    公开(公告)号：US20220352025A1

    公开(公告)日：2022-11-03

    申请号：US17865705

    申请日：2022-07-15

    Applicant: Micron Technology, Inc.

    Inventor： Po Chih Yang

    IPC: H01L21/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/268 ,  H01L21/304

    Abstract: A method for separating semiconductor dies of a semiconductor die assembly comprises depositing a first coating on a first surface of the assembly. The assembly comprises a die wafer having a plurality of semiconductor dies and first and second surfaces. A first portion of the die wafer and the first coating is removed between adjacent semiconductor dies to form trenches having an intermediate depth in the die wafer between first and second surfaces such that die corners are formed on either side of the trenches. A protective coating is deposited on the first surface of the die assembly to cover the die corners, trenches and at least a portion of the first coating. The first coating is selectively removed such that portions of the protective coating covering die corners and trenches remain on the die wafer. Adjacent semiconductor dies are separated and the protective coating remains covering the die corners.

    STRUCTURES AND METHODS FOR DICING SEMICONDUCTOR DEVICES
    2.
    发明公开
    STRUCTURES AND METHODS FOR DICING SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20230290684A1

    公开(公告)日：2023-09-14

    申请号：US17690981

    申请日：2022-03-09

    Applicant: Micron Technology, Inc.

    Inventor： Wei Chang Wong ,  Radhakrishna Kotti ,  Raj K. Bansal ,  Youngik Kwon ,  Po Chih Yang ,  Venkateswarlu Bhavanasi

    IPC: H01L21/78 ,  H01L23/58

    CPC classification number: H01L21/78 ,  H01L23/585 ,  H01L27/108

    Abstract: Structures and methods for separating semiconductor wafers into individual dies are disclosed. A semiconductor wafer or panel can include a crack assist structure in a scribe junction. The crack assist structure can include a plurality of vertical walls extending at least partially through a thickness of the wafer. In some embodiments, the plurality of vertical walls can be coupled to a weak interface. The weak interface can guide cracks that form during the dicing process in a direction along the walls, away from active circuitry. After dicing, the resulting semiconductor devices can include a plurality of vertical walls extending at least partially through a thickness of the semiconductor device. Each of the plurality of vertical walls can include at least a portion extending substantially parallel to a sidewall of the semiconductor device.

    DIE CORNER PROTECTION BY USING POLYMER DEPOSITION TECHNOLOGY
    3.
    发明申请
    DIE CORNER PROTECTION BY USING POLYMER DEPOSITION TECHNOLOGY 有权

    公开(公告)号：US20210391216A1

    公开(公告)日：2021-12-16

    申请号：US16901485

    申请日：2020-06-15

    Applicant: Micron Technology, Inc.

    Inventor： Po Chih Yang

    IPC: H01L21/78 ,  H01L21/02 ,  H01L21/268 ,  H01L21/304 ,  H01L21/3065

    Abstract: A method for separating semiconductor dies of a semiconductor die assembly comprises depositing a first coating on a first surface of the assembly. The assembly comprises a die wafer having a plurality of semiconductor dies and first and second surfaces. A first portion of the die wafer and the first coating is removed between adjacent semiconductor dies to form trenches having an intermediate depth in the die wafer between first and second surfaces such that die corners are formed on either side of the trenches. A protective coating is deposited on the first surface of the die assembly to cover the die corners, trenches and at least a portion of the first coating. The first coating is selectively removed such that portions of the protective coating covering die corners and trenches remain on the die wafer. Adjacent semiconductor dies are separated and the protective coating remains covering the die corners.

    Techniques for forming semiconductor device packages and related packages, intermediate products, and methods
    5.
    发明授权
    Techniques for forming semiconductor device packages and related packages, intermediate products, and methods 有权

    公开(公告)号：US11171109B2

    公开(公告)日：2021-11-09

    申请号：US16578975

    申请日：2019-09-23

    Applicant: Micron Technology, Inc.

    Inventor： Po Chih Yang ,  Yu Jen Chen ,  Po Chen Kuo ,  Shih Wei Liang

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L21/768 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31

    Abstract: Semiconductor device packages may include a first semiconductor device over a substrate and a second semiconductor device over the first semiconductor device. An active surface of the second semiconductor device may face away from the substrate. Electrical interconnections may extend from bond pads of the second semiconductor device, along surfaces of the second semiconductor device, first semiconductor device, and substrate to pads of routing members of the substrate. The electrical interconnections may include conductors in contact with the bond pads and the routing members and a dielectric material interposed between the conductors and the first semiconductor device, the second semiconductor device and the substrate between the bond pads and the pad of the routing members. An encapsulant distinct from the dielectric material may cover the electrical interconnections, the first semiconductor device, the second semiconductor device, and an upper surface of the substrate. Methods of fabrication are also disclosed.

    Die corner protection by using polymer deposition technology
    7.
    发明授权
    Die corner protection by using polymer deposition technology 有权

    公开(公告)号：US12046513B2

    公开(公告)日：2024-07-23

    申请号：US17865705

    申请日：2022-07-15

    Applicant: Micron Technology, Inc.

    Inventor： Po Chih Yang

    IPC: H01L21/78 ,  H01L21/02 ,  H01L21/268 ,  H01L21/304 ,  H01L21/3065

    CPC classification number: H01L21/78 ,  H01L21/0212 ,  H01L21/0217 ,  H01L21/268 ,  H01L21/304 ,  H01L21/3065

    Abstract: A method for separating semiconductor dies of a semiconductor die assembly comprises depositing a first coating on a first surface of the assembly. The assembly comprises a die wafer having a plurality of semiconductor dies and first and second surfaces. A first portion of the die wafer and the first coating is removed between adjacent semiconductor dies to form trenches having an intermediate depth in the die wafer between first and second surfaces such that die corners are formed on either side of the trenches. A protective coating is deposited on the first surface of the die assembly to cover the die corners, trenches and at least a portion of the first coating. The first coating is selectively removed such that portions of the protective coating covering die corners and trenches remain on the die wafer. Adjacent semiconductor dies are separated and the protective coating remains covering the die corners.

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