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公开(公告)号：US12141445B2
公开(公告)日：2024-11-12
申请号：US17960304
申请日：2022-10-05
Applicant: Micron Technology, Inc.
Inventor： Sheyang Ning , Lawrence Miranda
Abstract: Control logic in a memory device causes a first set of pulses corresponding to a first voltage ramp slope level to be applied to a memory cell during a first time interval of an execution of a memory access operation. In response to determining a transition time has been reached, the control logic causes a second set of pulses corresponding to a second voltage ramp slope level to be applied to the memory cell during a second time interval of the execution of the memory access operation, wherein the first voltage ramp slope level and the second voltage ramp slope level are different.
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公开(公告)号：US20240290389A1
公开(公告)日：2024-08-29
申请号：US18654697
申请日：2024-05-03
Applicant: Micron Technology, Inc.
Inventor： Sheyang Ning , Lawrence Celso Miranda , Zhengyi Zhang , Tomoko Ogura Iwasaki
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/3459
Abstract: Control logic in a memory device causes a programming pulse of a set of programming pulses to be applied to a wordline associated with a memory cell of a memory device, where the memory cell is to be programmed to a target voltage level representing a first programming level. At a first time, first data is caused to be stored in a cache, the first data indicating that a threshold voltage of a memory cell exceeds the target voltage level. At a second time, the cache is caused to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the target voltage level. In view of the second data, a level shifting operation associated with the memory cell is caused to be executed.
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公开(公告)号：US11961566B2
公开(公告)日：2024-04-16
申请号：US17833466
申请日：2022-06-06
Applicant: Micron Technology, Inc.
Inventor： Sheyang Ning , Lawrence Celso Miranda , Tomoko Ogura Iwasaki
CPC classification number: G11C16/16 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/3404 , G11C16/3481
Abstract: A memory device includes a first pillar coupled with a first data line, a second pillar coupled with a second data line, wordlines coupled with first and second pillars. Control logic is to cause: wordlines to be discharged after a program pulse is applied to selected wordline; a supply voltage be applied to second data line to cause a voltage of second pillar to float; a ground voltage be applied to first data line to inhibit soft erase via first pillar; unselected wordlines be charged to boost channel voltages in memory cells coupled with the second pillar; and one of the ground voltage or a negative voltage be applied to the selected wordline to increase soft erase voltage between a channel of a memory cell coupled with the second pillar and the selected wordline, causing a threshold voltage stored in the memory cell to be erased.
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公开(公告)号：US20230026558A1
公开(公告)日：2023-01-26
申请号：US17960304
申请日：2022-10-05
Applicant: Micron Technology, Inc.
Inventor： Sheyang Ning , Lawrence Miranda
Abstract: Control logic in a memory device causes a first set of pulses corresponding to a first voltage ramp slope level to be applied to a memory cell during a first time interval of an execution of a memory access operation. In response to determining a transition time has been reached, the control logic causes a second set of pulses corresponding to a second voltage ramp slope level to be applied to the memory cell during a second time interval of the execution of the memory access operation, wherein the first voltage ramp slope level and the second voltage ramp slope level are different.
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公开(公告)号：US20220351789A1
公开(公告)日：2022-11-03
申请号：US17306347
申请日：2021-05-03
Applicant: Micron Technology, Inc.
Inventor： Sheyang Ning , Lawrence Celso Miranda , Tomoko Ogura Iwasaki
Abstract: Described are systems and methods for reducing maximum programming voltage in memory programming operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying one or more memory cells for performing a memory programming operation, wherein the memory cells are electrically coupled to a target wordline and one or more target bitlines; causing drain-side select gates and source-side select gates of the memory array to be turned off; causing unselected wordlines of the memory array to discharge to a predefined voltage level; and causing one or more programming voltage pulses to be applied to the target wordline.
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Patent Agency Ranking
公开(公告)号：US20220310167A1
公开(公告)日：2022-09-29
申请号：US17675447
申请日：2022-02-18
Applicant: Micron Technology, Inc.
Inventor： Sheyang Ning , Lawrence Celso Miranda
Abstract: Control logic in a memory device identifies a set of a plurality of memory cells configured as multi-level cell (MLC) memory to be programmed during a program operation and causes, at a first time during a program operation, a first programming pulse to be applied to a memory cell of the memory array to be programmed to a first programming level. The control logic further performs a program verify operation corresponding to the first programming level and compares a threshold voltage of the memory cell to one or more program verify voltage levels of the program verify operation to determine whether a condition is satisfied. The control logic further executes a level shifting operation in response to the condition to be satisfied.
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公开(公告)号：US12211552B2
公开(公告)日：2025-01-28
申请号：US18121846
申请日：2023-03-15
Applicant: Micron Technology, Inc.
Inventor： Lawrence Celso Miranda , Tomoko Ogura Iwasaki , Sheyang Ning , Jeffrey S. McNeil
Abstract: Described are systems and methods for concurrent slow-fast memory cell programming. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying a set of memory cells for performing a memory programming operation, wherein the set of memory cells are electrically coupled to a target wordline and one or more target bitlines; causing a first programming pulse to be performed by applying a first programming voltage to the target wordline; classifying, by a processing device, the set of memory cells into a first subset of memory cells and a second subset of memory cells based on their respective threshold voltages; causing a first bias voltage to be applied to a first target bitline connected to the first subset of memory cells; causing a second bias voltage to be applied to a second target bitline connected to the second subset of memory cells; and causing a second programing voltage to be applied to the target wordline, wherein the second programming voltage exceeds the first programing voltage.
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公开(公告)号：US20240339158A1
公开(公告)日：2024-10-10
申请号：US18625800
申请日：2024-04-03
Applicant: Micron Technology, Inc.
Inventor： Sheyang Ning , Lawrence Celso Miranda , Jeffrey S. McNeil , Tomoko Ogura Iwasaki , Yeang Meng Hern , Lee-eun Yu , Albert Fayrushin , Fulvio Rori , Justin Bates
CPC classification number: G11C16/08 , G11C16/0483 , G11C16/10
Abstract: Control logic in a memory device initiates a program operation including a first phase including applying a ramping voltage level to a set of wordlines of a memory device to boost a set of pillar voltages and a second phase including applying a set of programming pulses to a wordline associated with one or more memory cells of the memory device to be programmed to a set of programming levels, wherein each programming level of the set of programming levels is programmed by each programming pulse. During the first phase of the program operation, a first voltage applied to a drain-side select line (SGD) is adjusted from a first SGD voltage level to a second SGD voltage level.
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公开(公告)号：US11664079B2
公开(公告)日：2023-05-30
申请号：US17940338
申请日：2022-09-08
Applicant: Micron Technology, Inc.
Inventor： Lawrence Celso Miranda , Eric N. Lee , Tong Liu , Sheyang Ning , Cobie B. Loper , Ugo Russo
CPC classification number: G11C16/3459 , G11C16/0483 , G11C16/10 , G11C16/06
Abstract: Control logic in a memory device executes a first operation comprising a first set of programming pulses and a first set of program verify operations on a first portion of a first subset of memory cells to be programmed to identify a first start voltage level. A second set of programming pulses including at least one programming pulse having the first start voltage level is caused to be applied to program a second portion of the first subset of memory cells. A second operation including a third set of programming pulses and a second set of program verify operations are executed on a first portion of the second subset of memory cells to identify a second start voltage level.
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公开(公告)号：US20230162793A1
公开(公告)日：2023-05-25
申请号：US18095049
申请日：2023-01-10
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Hao T. Nguyen , Tomoko Ogura Iwasaki , Erwin E. Yu , Dheeraj Srinivasan , Sheyang Ning , Lawrence Celso Miranda , Aaron S. Yip , Yoshihiko Kamata
CPC classification number: G11C16/0483 , G11C16/10 , G11C16/3459 , G11C16/26 , G11C11/5671
Abstract: Memory devices might include a first storage element, a second storage element, a data line, and a controller. The first storage element is to store a first data bit. The second storage element is to store a second data bit. The data line is selectively connected to the first storage element, the second storage element, and a memory cell. The controller is configured to apply one of four voltage levels to the data line based on the first data bit and the second data bit.
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