公开(公告)号：US11626423B2

公开(公告)日：2023-04-11

申请号：US17373278

申请日：2021-07-12

Applicant: Micron Technology, Inc.

Inventor： Xiaosong Zhang ,  Yi Hu ,  Tom J. John ,  Wei Yeeng Ng ,  Chandra Tiwari

IPC: H01L21/311 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

Abstract: In some embodiments, a memory array comprising strings of memory cells comprise laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The pillars comprise vertically-spaced and radially-projecting insulative rings in the conductive tiers as compared to the insulative tiers. Other embodiments, including methods, are disclosed.

公开(公告)号：US11520240B2

公开(公告)日：2022-12-06

申请号：US17314410

申请日：2021-05-07

Applicant: Micron Technology, Inc.

Inventor： Nikolay A. Mirin ,  Robert Dembi ,  Richard T. Housley ,  Xiaosong Zhang ,  Jonathan D. Harms ,  Stephen J. Kramer

IPC: G03F7/20 ,  H01L21/68 ,  G01R33/07 ,  H01L23/544

Abstract: A method of aligning a wafer for semiconductor fabrication processes may include applying a magnetic field to a wafer, detecting one or more residual magnetic fields from one or more alignment markers within the wafer, responsive to the detected one or more residual magnetic fields, determining locations of the one or more alignment markers. The marker locations may be determined relative to an ideal grid, followed by determining a geometrical transformation model for aligning the wafer, and aligning the wafer responsive to the geometrical transformation model. Related methods and systems are also disclosed.

公开(公告)号：US12178045B2

公开(公告)日：2024-12-24

申请号：US18158576

申请日：2023-01-24

Applicant: Micron Technology, Inc.

Inventor： Md Zakir Ullah ,  Xiaosong Zhang ,  Adam L. Olson ,  Mohammad Moydul Islam ,  Tien Minh Quan Tran ,  Chao Zhu ,  Zhigang Yang ,  Merri L. Carlson ,  Hui Chin Chong ,  David A. Kewley ,  Kok Siak Tang

IPC: H10B43/27 ,  H10B41/27

Abstract: Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. First and second arrays of pillars extend through the stack structure of the lower and upper decks, respectively. In one or more of the first and second pillar arrays, at least some pillars exhibit a greater degree of bending away from a vertical orientation than at least some other pillars. The pillars of the first array align with the pillars of the second array along an interface between the lower and upper decks. Related methods are also disclosed.

公开(公告)号：US20230209827A1

公开(公告)日：2023-06-29

申请号：US18116946

申请日：2023-03-03

Applicant: Micron Technology, Inc.

Inventor： Xiaosong Zhang ,  Yi Hu ,  Tom J. John ,  Wei Yeeng Ng ,  Chandra Tiwari

IPC: H10B43/27 ,  H01L21/311 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H01L21/31111 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: In some embodiments, a memory array comprising strings of memory cells comprise laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The pillars comprise vertically-spaced and radially-projecting insulative rings in the conductive tiers as compared to the insulative tiers. Other embodiments, including methods, are disclosed.

公开(公告)号：US20230063178A1

公开(公告)日：2023-03-02

申请号：US17564633

申请日：2021-12-29

Applicant: Micron Technology, Inc.

Inventor： Bo Zhao ,  Matthew J. King ,  Jason Reece ,  Michael J. Gossman ,  Shruthi Kumara Vadivel ,  Martin J. Barclay ,  Lifang Xu ,  Joel D. Peterson ,  Matthew Park ,  Adam L. Olson ,  David A. Kewley ,  Xiaosong Zhang ,  Justin B. Dorhout ,  Zhen Feng Yow ,  Kah Sing Chooi ,  Tien Minh Quan Tran ,  Biow Hiem Ong

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: A microelectronic device includes a stack structure including a vertically alternating sequence of conductive structures and insulating structures arranged in tiers, a dielectric-filled opening vertically extending into the stack structure and defined between two internal sidewalls of the stack structure, a stadium structure within the stack structure and comprising steps defined by horizontal ends of at least some of the tiers, a first ledge extending upward from a first uppermost step of the steps of the stadium structure and interfacing with a first internal sidewall of the two internal sidewalls of the stack structure, and a second ledge extending upward from a second, opposite uppermost step of the steps of the stadium structure and interfacing with a second, opposite internal sidewall of the two internal sidewalls.

公开(公告)号：US20210399012A1

公开(公告)日：2021-12-23

申请号：US17373278

申请日：2021-07-12

Applicant: Micron Technology, Inc

Inventor： Xiaosong Zhang ,  Yi Hu ,  Tom J. John ,  Wei Yeeng Ng ,  Chandra Twari

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L21/311 ,  H01L27/11519

Abstract: In some embodiments, a memory array comprising strings of memory cells comprise laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The pillars comprise vertically-spaced and radially-projecting insulative rings in the conductive tiers as compared to the insulative tiers. Other embodiments, including methods, are disclosed.

公开(公告)号：US11205654B2

公开(公告)日：2021-12-21

申请号：US16550238

申请日：2019-08-25

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Ramey M. Abdelrahaman ,  Narula Bilik ,  Daniel Billingsley ,  Zhenyu Bo ,  Joan M. Kash ,  Matthew J. King ,  Andrew Li ,  David Neumeyer ,  Wei Yeeng Ng ,  Yung K. Pak ,  Chandra Tiwari ,  Yiping Wang ,  Lance Williamson ,  Xiaosong Zhang

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1157

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.

公开(公告)号：US20200119032A1

公开(公告)日：2020-04-16

申请号：US16160342

申请日：2018-10-15

Applicant: Micron Technology Inc.

Inventor： Yi Hu ,  Jian Li ,  Lifang Xu ,  Xiaosong Zhang

IPC: H01L27/11565 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768

Abstract: In an example, a method of forming a stacked memory array includes, forming a termination structure passing through a stack of alternating first and second dielectrics in a first region of the stack; forming first and second sets of contacts through the stack of alternating first and second dielectrics in a second region of the stack concurrently with forming the termination structure; forming an opening through the stack of alternating first and second dielectrics between the first and second sets of contacts so that the opening terminates at the termination structure; and removing the first dielectrics from the second region by accessing the first dielectrics through the opening so that the first and second sets of contacts pass through the second dielectrics alternating with spaces corresponding to the removed first dielectrics.

公开(公告)号：US20240064988A1

公开(公告)日：2024-02-22

申请号：US17900455

申请日：2022-08-31

Applicant: Micron Technology, Inc.

Inventor： Md Zahid Hossain ,  Martin Popp ,  Xiaosong Zhang ,  Surendranath C. Eruvuru ,  Suvra Sarkar ,  Tianqi Xu

IPC: H01L27/11573 ,  H01L27/11526

CPC classification number: H01L27/11573 ,  H01L27/11526

Abstract: A variety of applications can include apparatus having a memory device structured with a circuit under array (CuA) architecture. A page buffer region in the CuA can be formed with a periphery region that is horizontally adjacent to the page buffer region. Contacts to gates for transistors in the page buffer region can be formed to land only on these gates, separating and electrically isolating the contacts and associated gates from each other in the page buffer region. Contacts to gates for transistors in the periphery region can be formed to land on conductive regions disposed on gates for transistors in the periphery region.

公开(公告)号：US11563027B2

公开(公告)日：2023-01-24

申请号：US17016002

申请日：2020-09-09

Applicant: Micron Technology, Inc.

Inventor： Md Zakir Ullah ,  Xiaosong Zhang ,  Adam L. Olson ,  Mohammad Moydul Islam ,  Tien Minh Quan Tran ,  Chao Zhu ,  Zhigang Yang ,  Merri L. Carlson ,  Hui Chin Chong ,  David A. Kewley ,  Kok Siak Tang

IPC: H01L27/11582 ,  H01L27/11556

Abstract: Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A lower array of pillars extends through the stack structure of the lower deck, and an upper array of pillars extends through the stack structure of the upper deck. Along an interface between the lower deck and the upper deck, the pillars of the lower array align with the pillars of the upper array. At least at elevations comprising bases of the pillars, a pillar density of the pillars of the lower array differs from a pillar density of the pillars of the upper array, “pillar density” being a number of pillars per unit of horizontal area of the respective array. Related methods and electronic systems are also disclosed.