公开(公告)号：US20190115340A1

公开(公告)日：2019-04-18

申请号：US15783232

申请日：2017-10-13

Applicant: NXP B.V.

Inventor： Jan Claes ,  Stephen John Sque ,  Maarten Jacobus Swanenberg ,  Da-Wei Lai

IPC: H01L27/02 ,  H01L27/07 ,  H01L29/10 ,  H01L29/735

CPC classification number: H01L27/0277 ,  H01L27/0259 ,  H01L27/0705 ,  H01L29/1008 ,  H01L29/735

Abstract: Various embodiments are directed to electrostatic discharge (ESD) protection apparatus comprising a bipolar junction transistor (BJT) having terminals, a field-effect transistor (FET) having terminals, and a common base region connected to a recombination region. The BJT and the FET are integrated with one another and include a common region that is shared by the BJT and the FET. The BJT and FET collectively bias the common base region and prevent triggering of the BJT by causing a potential of the common base region to follow a potential of one of the terminals of the BJT in response to an excessive but tolerable non-ESD voltage change at one or more of the terminals.

公开(公告)号：US09653447B2

公开(公告)日：2017-05-16

申请号：US14495468

申请日：2014-09-24

Applicant: NXP B.V.

Inventor： Albert Jan Huitsing ,  Jan Claes

IPC: H01L29/10 ,  H01L27/02 ,  H01L27/082 ,  H01L23/535 ,  H01L23/367 ,  H01L27/12 ,  H01L21/8222 ,  H01L29/417

CPC classification number: H01L27/0248 ,  H01L21/8222 ,  H01L23/367 ,  H01L23/535 ,  H01L27/0259 ,  H01L27/082 ,  H01L27/1203 ,  H01L29/41708 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a PNP ESD integrated circuit, including a substrate, an active region formed within the substrate, the active region including at least one base region of a second conductivity type, a plurality of collector regions of a first conductivity type formed within the active region, a plurality of emitter regions of the first conductivity type formed within the active region, and a local interconnect layer (LIL) contacting the plurality of emitter regions and the plurality of collector regions, the LIL including cooling fin contacts formed on the collector regions to enhance the current handling capacity of the collector regions.

公开(公告)号：US20160086934A1

公开(公告)日：2016-03-24

申请号：US14495468

申请日：2014-09-24

Applicant: NXP B.V.

Inventor： Albert Jan Huitsing ,  Jan Claes

IPC: H01L27/02 ,  H01L21/8222 ,  H01L23/367 ,  H01L27/12 ,  H01L27/082 ,  H01L23/535

CPC classification number: H01L27/0248 ,  H01L21/8222 ,  H01L23/367 ,  H01L23/535 ,  H01L27/0259 ,  H01L27/082 ,  H01L27/1203 ,  H01L29/41708 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a PNP ESD integrated circuit, including a substrate, an active region formed within the substrate, the active region including at least one base region of a second conductivity type, a plurality of collector regions of a first conductivity type formed within the active region, a plurality of emitter regions of the first conductivity type formed within the active region, and a local interconnect layer (LIL) contacting the plurality of emitter regions and the plurality of collector regions, the LIL including cooling fin contacts formed on the collector regions to enhance the current handling capacity of the collector regions.

Abstract translation: 公开了一种PNP ESD集成电路，包括：衬底，形成在衬底内的有源区，有源区包括至少一个第二导电类型的基极区;多个第一导电类型的集电极区，形成在有源区内 ，在有源区内形成的第一导电类型的多个发射极区域和与多个发射极区域和多个集电极区域接触的局部互连层（LIL），LIL包括形成在集电区域上的冷却翅片触点， 提升收集区目前的处理能力。

公开(公告)号：US08981442B2

公开(公告)日：2015-03-17

申请号：US14108106

申请日：2013-12-16

Applicant: NXP B.V.

Inventor： Victor Zieren ,  Anco Heringa ,  Olaf Wunnicke ,  Jan Slotboom ,  Robert Hendrikus Margaretha van Veldhoven ,  Jan Claes

IPC: H01L29/82 ,  H01L43/02 ,  G01R33/06 ,  H01L29/735 ,  H01L29/861

CPC classification number: H01L43/02 ,  G01R33/066 ,  H01L29/735 ,  H01L29/82 ,  H01L29/8611

Abstract: A semiconductor magnetic field sensor comprising a semiconductor well on top of a substrate layer is disclosed. The semiconductor well includes a first current collecting region and a second current collecting region and a current emitting region placed between the first current collecting region and the second current collecting region. The semiconductor well also includes a first MOS structure, having a first gate terminal, located between the first current collecting region and the current emitting region and a second MOS structure, having a second gate terminal, located between the current emitting region and the second current collecting region. In operation, the first gate terminal and the second gate terminal are biased for increasing a deflection length of a first current and of a second current. The deflection length is perpendicular to a plane defined by a surface of the semiconductor magnetic field sensor and parallel to a magnetic field.

Abstract translation: 公开了一种半导体磁场传感器，其包括在衬底层顶部的半导体阱。 半导体阱包括第一集电区域和第二集电区域以及放置在第一集电区域和第二集电区域之间的电流发射区域。 半导体阱还包括第一MOS结构，其具有位于第一集电区和电流发射区之间的第一栅极端子和第二MOS结构，具有位于电流发射区和第二电流之间的第二栅极端 收集区域。 在操作中，第一栅极端子和第二栅极端子被偏置以增加第一电流和第二电流的偏转长度。 偏转长度垂直于由半导体磁场传感器的表面限定并平行于磁场的平面。

公开(公告)号：US20140175528A1

公开(公告)日：2014-06-26

申请号：US14108106

申请日：2013-12-16

Applicant: NXP B.V.

Inventor： Victor Zieren ,  Anco Heringa ,  Olaf Wunnicke ,  Jan Slotboom ,  Robert Hendrikus Margaretha van Veldhoven ,  Jan Claes

IPC: H01L43/02

CPC classification number: H01L43/02 ,  G01R33/066 ,  H01L29/735 ,  H01L29/82 ,  H01L29/8611

Abstract: A semiconductor magnetic field sensor comprising a semiconductor well on top of a substrate layer is disclosed. The semiconductor well includes a first current collecting region and a second current collecting region and a current emitting region placed between the first current collecting region and the second current collecting region. The semiconductor well also includes a first MOS structure, having a first gate terminal, located between the first current collecting region and the current emitting region and a second MOS structure, having a second gate terminal, located between the current emitting region and the second current collecting region. In operation, the first gate terminal and the second gate terminal are biased for increasing a deflection length of a first current and of a second current. The deflection length is perpendicular to a plane defined by a surface of the semiconductor magnetic field sensor and parallel to a magnetic field.

Abstract translation: 公开了一种半导体磁场传感器，其包括在衬底层顶部的半导体阱。 半导体阱包括第一集电区域和第二集电区域以及放置在第一集电区域和第二集电区域之间的电流发射区域。 半导体阱还包括第一MOS结构，其具有位于第一集电区和电流发射区之间的第一栅极端子和第二MOS结构，具有位于电流发射区和第二电流之间的第二栅极端 收集区域。 在操作中，第一栅极端子和第二栅极端子被偏置以增加第一电流和第二电流的偏转长度。 偏转长度垂直于由半导体磁场传感器的表面限定并平行于磁场的平面。

公开(公告)号：US10475783B2

公开(公告)日：2019-11-12

申请号：US15783232

申请日：2017-10-13

Applicant: NXP B.V.

Inventor： Jan Claes ,  Stephen John Sque ,  Maarten Jacobus Swanenberg ,  Da-Wei Lai

IPC: H01L27/02 ,  H01L29/735 ,  H01L29/10 ,  H01L27/07

Abstract: Various embodiments are directed to electrostatic discharge (ESD) protection apparatus comprising a bipolar junction transistor (BJT) having terminals, a field-effect transistor (FET) having terminals, and a common base region connected to a recombination region. The BJT and the FET are integrated with one another and include a common region that is shared by the BJT and the FET. The BJT and FET collectively bias the common base region and prevent triggering of the BJT by causing a potential of the common base region to follow a potential of one of the terminals of the BJT in response to an excessive but tolerable non-ESD voltage change at one or more of the terminals.

公开(公告)号：US10134860B2

公开(公告)日：2018-11-20

申请号：US15456963

申请日：2017-03-13

Applicant: NXP B.V.

Inventor： Jan Sonsky ,  Viet Thanh Dinh ,  Jan Claes

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes a first dielectric layer on a substrate, the first dielectric layer including a first dielectric portion over a first doped well region of a first conductivity type and a second dielectric portion over a second doped well region of a second conductivity type, and a second dielectric layer on the substrate directly adjacent the first dielectric layer. The second dielectric layer is over the second doped well region. A first conductive gate structure is over the first and second dielectric layers. A third dielectric layer is on the substrate over the second doped well region and separated a first distance from the second dielectric layer. A second conductive gate structure is over the third dielectric layer. A third doped region of the second conductivity type is implanted in the second doped well region a second distance from the third dielectric layer and the second conductive gate structure.