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    Shielded QFN package and method of making
    3.
    发明授权
    Shielded QFN package and method of making 有权

    公开(公告)号：US10096555B2

    公开(公告)日：2018-10-09

    申请号：US15464016

    申请日：2017-03-20

    Applicant: NXP B.V.

    Inventor： Jan Gulpen ,  Leonardus Antonius Elisabeth van Gemert

    IPC: H01L21/78 ,  H01L21/48 ,  H01L23/552 ,  H01L23/60 ,  H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/52 ,  H01L21/3205 ,  H01L23/00

    Abstract: Consistent with an example embodiment, a semiconductor device comprises a device die having bond pads providing connection to device die circuitry and a QFN half-etched lead frame with a package boundary; the QFN half-etched lead frame has a top-side surface and an under-side surface. The QFN half-etched lead frame includes a sub-structure of I/O terminals and a die attach area, the die attach area facilitating device die attachment thereon and the terminal I/O terminals providing connection to the device die bond pads and additional terminals located about the corners of the sub-structure. An envelope of molding compound encapsulates the device die mounted on the top-side surface of the QFN half-etched lead frame. A RF (radio-frequency) shield layer is on the envelope of the molding compound, the RF shield electrically connected to the additional terminals via conductive connections defined in corresponding locations on the envelope of the molding compound.

    Method of making a plurality of packaged semiconductor devices
    5.
    发明授权
    Method of making a plurality of packaged semiconductor devices 有权

    公开(公告)号：US10431476B2

    公开(公告)日：2019-10-01

    申请号：US15935187

    申请日：2018-03-26

    Applicant: NXP B.V.

    Inventor： Jetse de Witte ,  Antonius Hendrikus Jozef Kamphuis ,  Jan Gulpen

    IPC: H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L21/683 ,  H01L23/31 ,  H01L23/495 ,  G01R31/28 ,  H01L21/66

    Abstract: A method of making a plurality of packaged semiconductor devices. The method includes providing a carrier blank having a die receiving surface and an underside. The method also includes mounting a plurality of semiconductor dies on the die receiving surface, wherein the dies extend to a first height above the die receiving surface. The method further includes depositing an encapsulant on the die receiving surface, wherein an upper surface of the encapsulant is located above said first height. The method also includes singulating to form the plurality of packaged semiconductor devices by sawing into the underside, through the carrier blank and partially through the encapsulant to a depth intermediate the first height and the upper surface, wherein said sawing separates the carrier blank into a plurality of carriers, and removing encapsulant from the upper surface of the encapsulant at least until said saw depth is reached.

    Wafer level chip scale semiconductor package
    7.
    发明授权
    Wafer level chip scale semiconductor package 有权

    公开(公告)号：US10109564B2

    公开(公告)日：2018-10-23

    申请号：US15431124

    申请日：2017-02-13

    Applicant: NXP B.V.

    Inventor： Roelf Groenhuis ,  Leo Van Gemert ,  Tonny Kamphuis ,  Jan Gulpen

    IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

    Abstract: This disclosure relates to a method of forming a wafer level chip scale semiconductor package, the method comprising: providing a carrier having a cavity formed therein; forming electrical contacts at a base portion and sidewalls portions of the cavity; placing a semiconductor die in the base of the cavity; connecting bond pads of the semiconductor die to the electrical contacts; encapsulating the semiconductor die; and removing the carrier to expose the electrical contacts, such that the electrical contacts are arranged directly on the encapsulation material.

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