公开(公告)号：US09892039B2

公开(公告)日：2018-02-13

申请号：US14691971

申请日：2015-04-21

Applicant: Oracle International Corporation

Inventor： Mark Luttrell ,  David Smentek ,  Ramaswamy Sivaramakrishnan ,  Serena Leung

IPC: G06F12/00 ,  G06F12/0811 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/0831

CPC classification number: G06F12/0811 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/128 ,  G06F2212/283 ,  G06F2212/622

Abstract: A method and apparatus for performing non-temporal write combining using existing cache resources is disclosed. In one embodiment, a method includes executing a first thread on a processor core, the first thread including a first block initialization store (BIS) instruction. A cache query may be performed responsive to the BIS instruction, and if the query results in a cache miss, a cache line may be installed in a cache in an unordered dirty state in which it is exclusively owned by the first thread. The first BIS instruction and one or more additional BIS instructions may write data from the first processor core into the first cache line. After a cache coherence response is received, the state of the first cache line may be changed to an ordered dirty state in which it is no longer exclusive to the first thread.

公开(公告)号：US08972663B2

公开(公告)日：2015-03-03

申请号：US13830967

申请日：2013-03-14

Applicant: Oracle International Corporation

Inventor： Paul N. Loewenstein ,  Stephen E. Phillips ,  David Richard Smentek ,  Connie Wai Mun Cheung ,  Serena Wing Yee Leung ,  Damien Walker ,  Ramaswamy Sivaramakrishnan

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0808 ,  G06F12/0811 ,  G06F12/0817 ,  G06F12/0828

Abstract: A method for cache coherence, including: broadcasting, by a requester cache (RC) over a partially-ordered request network (RN), a peer-to-peer (P2P) request for a cacheline to a plurality of slave caches; receiving, by the RC and over the RN while the P2P request is pending, a forwarded request for the cacheline from a gateway; receiving, by the RC and after receiving the forwarded request, a plurality of responses to the P2P request from the plurality of slave caches; setting an intra-processor state of the cacheline in the RC, wherein the intra-processor state also specifies an inter-processor state of the cacheline; and issuing, by the RC, a response to the forwarded request after setting the intra-processor state and after the P2P request is complete; and modifying, by the RC, the intra-processor state in response to issuing the response to the forwarded request.

Abstract translation: 一种用于高速缓存一致性的方法，包括：通过部分有序请求网络（RN）的请求者缓存（RC）广播对多个从高速缓存的高速缓存线的对等（P2P）请求; 当P2P请求正在等待时，由RC接收和通过RN接收来自网关的高速缓存行的转发请求; 由所述RC接收所述转发请求后，从所述多个从属高速缓存中接收对所述P2P请求的多个响应; 在所述RC中设置所述高速缓存行的处理器内状态，其中所述处理器内状态还指定所述高速缓存行的处理器间状态; 以及在设置处理器内状态之后，在P2P请求完成之后，由RC发出对转发请求的响应; 以及响应于发出对所转发的请求的响应，由RC修改处理器内状态。

公开(公告)号：US20160019149A1

公开(公告)日：2016-01-21

申请号：US14584755

申请日：2014-12-29

Applicant: Oracle International Corporation

Inventor： Ramaswamy Sivaramakrishnan ,  Serena Leung ,  David Smentek

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0862 ,  G06F2212/1024 ,  G06F2212/6024 ,  Y02D10/13

Abstract: A cache memory that selectively enables and disables speculative reads from system memory is disclosed. The cache memory may include a plurality of partitions, and a plurality of registers. Each register may be configured to stored data indicative of a source of returned data for previous requests directed to a corresponding partition. Circuitry may be configured to receive a request for data to a given partition. The circuitry may be further configured to read contents of a register corresponding to the given partition, and initiate a speculative read dependent upon the contents of the register.

Abstract translation: 公开了一种高速缓冲存储器，其选择性地启用和禁用来自系统存储器的推测性读取。 高速缓存存储器可以包括多个分区和多个寄存器。 每个寄存器可以被配置为存储指示针对相应分区的先前请求的返回数据的源的数据。 电路可以被配置为接收对给定分区的数据请求。 电路还可以被配置为读取与给定分区相对应的寄存器的内容，并且依赖于寄存器的内容来启动推测读取。

公开(公告)号：US20140181420A1

公开(公告)日：2014-06-26

申请号：US13758491

申请日：2013-02-04

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Thomas M. Wicki ,  Stephen E. Phillips ,  Nicholas E. Aneshansley ,  Ramaswamy Sivaramakrishnan ,  Paul N. Loewenstein

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F11/07 ,  G06F11/14 ,  G06F12/0824

Abstract: A system includes a number of processors with each processor including a cache memory. The system also includes a number of directory controllers coupled to the processors. Each directory controller may be configured to administer a corresponding cache coherency directory. Each cache coherency directory may be configured to track a corresponding set of memory addresses. Each processor may be configured with information indicating the corresponding set of memory addresses tracked by each cache coherency directory. Directory redundancy operations in such a system may include identifying a failure of one of the cache coherency directories; reassigning the memory address set previously tracked by the failed cache coherency directory among the non-failed cache coherency directories; and reconfiguring each processor with information describing the reassignment of the memory address set among the non-failed cache coherency directories.

Abstract translation: 系统包括多个处理器，每个处理器包括高速缓冲存储器。 该系统还包括耦合到处理器的多个目录控制器。 每个目录控制器可以被配置为管理对应的高速缓存一致性目录。 每个高速缓存一致性目录可以被配置为跟踪相应的一组存储器地址。 每个处理器可以配置有指示由每个高速缓存一致性目录跟踪的对应的一组存储器地址的信息。 这种系统中的目录冗余操作可以包括识别高速缓存一致性目录之一的故障; 重新分配先前由非故障高速缓存一致性目录中的失败的高速缓存一致性目录跟踪的存储器地址集; 以及用描述非故障高速缓存一致性目录中的存储器地址集的重新分配的信息重新配置每个处理器。

公开(公告)号：US20190079795A1

公开(公告)日：2019-03-14

申请号：US15699027

申请日：2017-09-08

Applicant: Oracle International Corporation

Inventor： John R. Feehrer ,  Milton Shih ,  Matthew Cohen ,  Kenneth Chan ,  Ramaswamy Sivaramakrishnan ,  Julia Harper ,  Peter Dunlap

IPC: G06F9/48 ,  G06F13/42 ,  G06F11/07 ,  G06F21/60

Abstract: A method and system for processing data are disclosed. A processor, in response to executing a software program, may write an entry in a work queue. The entry may include an operation, and a location of data stored in an input buffer, and a location in an output buffer to write processed data. The processor may also generate a notification that at least one entry in the work queue is ready to be processed. The data transformation unit may assign the entry to a data transformation circuit, and retrieve the data from the input buffer using the location. The data transformation unit may also perform to the operation on the retrieved data to generate updated data, generate a completion message in response to completion of the operation, and store the updated data in an output buffer. An interface unit may relay transactions between the processor and the data transformation unit.

公开(公告)号：US09836406B2

公开(公告)日：2017-12-05

申请号：US14978007

申请日：2015-12-22

Applicant: Oracle International Corporation

Inventor： Serena Wing Yee Leung ,  Ramaswamy Sivaramakrishnan ,  Sumti Jairath

IPC: G06F12/12 ,  G06F12/0891 ,  G06F12/084 ,  G06F12/0895

CPC classification number: G06F12/0891 ,  G06F12/0804 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0895 ,  G06F12/121 ,  G06F12/126 ,  G06F2212/1024 ,  G06F2212/502 ,  G06F2212/62

Abstract: A method, system, and computer-readable medium for evicting cache lines that includes determining that a first cache line is to be evicted from a first Last Level Cache (LLC) partition of a partitioned LLC, and sending, based on the determination, a first notification to a second LLC partition of the partitioned LLC. The method may also include receiving, in response to the first notification, an available indication indicating that the second LLC partition is available as a designated victim cache partition; performing a selection of the second LLC partition as the designated victim cache partition; and evicting the first cache line to the second LLC partition based on the selection.

公开(公告)号：US10120800B2

公开(公告)日：2018-11-06

申请号：US14584755

申请日：2014-12-29

Applicant: Oracle International Corporation

Inventor： Ramaswamy Sivaramakrishnan ,  Serena Leung ,  David Smentek

IPC: G06F12/00 ,  G06F12/0811 ,  G06F12/0862

Abstract: A cache memory that selectively enables and disables speculative reads from system memory is disclosed. The cache memory may include a plurality of partitions, and a plurality of registers. Each register may be configured to stored data indicative of a source of returned data for previous requests directed to a corresponding partition. Circuitry may be configured to receive a request for data to a given partition. The circuitry may be further configured to read contents of a register corresponding to the given partition, and initiate a speculative read dependent upon the contents of the register.

公开(公告)号：US20160335184A1

公开(公告)日：2016-11-17

申请号：US14713053

申请日：2015-05-15

Applicant: Oracle International Corporation

Inventor： Serena Leung ,  Ramaswamy Sivaramakrishnan ,  Joann Lam ,  David Smentek

IPC: G06F12/08

CPC classification number: G06F12/0848 ,  G06F12/0802 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/0842 ,  G06F2212/282 ,  G06F2212/621

Abstract: A method and apparatus for snooping caches is disclosed. In one embodiment, a system includes a number of processing nodes and a cache shared by each of the processing nodes. The cache is partitioned such that each of the processing nodes utilizes only one assigned partition. If a query by a processing node to its assigned partition of the cache results in a miss, a cache controller may determine whether to snoop other partitions in search of the requested information. The determination may be made based on history of where requested information was obtained from responsive to previous misses in that partition.

Abstract translation: 公开了一种用于窥探高速缓存的方法和装置。 在一个实施例中，系统包括多个处理节点和由每个处理节点共享的高速缓存。 高速缓存被分区，使得每个处理节点仅使用一个分配的分区。 如果处理节点对其分配的缓存分区的查询导致错过，则高速缓存控制器可以确定是否窥探其他分区以搜索所请求的信息。 可以基于从该分区中的先前错过所获得的请求信息的历史来进行确定。

公开(公告)号：US20160314069A1

公开(公告)日：2016-10-27

申请号：US14691971

申请日：2015-04-21

Applicant: Oracle International Corporation

Inventor： Mark Luttrell ,  David Smentek ,  Ramaswamy Sivaramakrishnan ,  Serena Leung

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0811 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/128 ,  G06F2212/283 ,  G06F2212/622

Abstract: A method and apparatus for performing non-temporal write combining using existing cache resources is disclosed. In one embodiment, a method includes executing a first thread on a processor core, the first thread including a first block initialization store (BIS) instruction. A cache query may be performed responsive to the BIS instruction, and if the query results in a cache miss, a cache line may be installed in a cache in an unordered dirty state in which it is exclusively owned by the first thread. The first BIS instruction and one or more additional BIS instructions may write data from the first processor core into the first cache line. After a cache coherence response is received, the state of the first cache line may be changed to an ordered dirty state in which it is no longer exclusive to the first thread.

Abstract translation: 公开了一种使用现有高速缓存资源执行非时间写入组合的方法和装置。 在一个实施例中，一种方法包括执行处理器核心上的第一线程，第一线程包括第一块初始化存储（BIS）指令。 可以响应于BIS指令执行缓存查询，并且如果查询导致高速缓存未命中，则高速缓存行可以以无序的脏状态安装在高速缓存中，其中它是由第一线程专有的。 第一BIS指令和一个或多个附加BIS指令可以将数据从第一处理器核心写入第一高速缓存行。 在接收到高速缓存一致性响应之后，可以将第一高速缓存行的状态改变为不再对第一线程排斥的有序脏状态。

公开(公告)号：US09323600B2

公开(公告)日：2016-04-26

申请号：US14486776

申请日：2014-09-15

Applicant: Oracle International Corporation

Inventor： Ramaswamy Sivaramakrishnan ,  Ali Vahidsafa ,  Aaron S. Wynn ,  Connie W. Cheung

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/16 ,  G06F12/08 ,  G06F12/12 ,  G06F9/30 ,  G06F11/20

CPC classification number: G06F11/0793 ,  G06F9/30 ,  G06F9/30047 ,  G06F11/073 ,  G06F11/1666 ,  G06F11/20 ,  G06F12/0804 ,  G06F12/0844 ,  G06F12/0891 ,  G06F12/126 ,  G06F2212/1008 ,  G06F2212/1032

Abstract: The systems and methods described herein may provide a flush-retire instruction for retiring “bad” cache locations (e.g., locations associated with persistent errors) to prevent their allocation for any further accesses, and a flush-unretire instruction for unretiring cache locations previously retired. These instructions may be implemented as hardware instructions of a processor. They may be executable by processes executing in a hyper-privileged state, without the need to quiesce any other processes. The flush-retire instruction may atomically flush a cache line implicated by a detected cache error and set a lock bit to disable subsequent allocation of the corresponding cache location. The flush-unretire instruction may atomically flush an identified cache line (if valid) and clear the lock bit to re-enable subsequent allocation of the cache location. Various bits in the encodings of these instructions may identify the cache location to be retired or unretired in terms of the physical cache structure.

Abstract translation: 本文描述的系统和方法可以提供用于退出“不良”高速缓存位置（例如，与持续错误相关联的位置）的刷新退出指令，以防止其对任何进一步访问的分配，以及用于撤销先前退休的高速缓存位置的刷新指令 。 这些指令可以被实现为处理器的硬件指令。 它们可以由以超级特权状态执行的进程执行，而不需要使任何其他进程停顿。 刷新 - 退出指令可以原子地刷新由检测到的高速缓存错误所牵连的高速缓存行，并设置锁定位以禁用对应的高速缓存位置的后续分配。 flush-unretire指令可以原子地刷新已识别的高速缓存行（如果有效）并清除锁定位以重新启用高速缓存位置的后续分配。 这些指令的编码中的各个比特可以根据物理高速缓存结构来标识要退休或未退出的高速缓存位置。