公开(公告)号：US12074093B2

公开(公告)日：2024-08-27

申请号：US17630766

申请日：2020-08-21

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Manabu Yanagihara ,  Takahiro Sato ,  Hiroto Yamagiwa ,  Masahiro Hikita

IPC: H01L21/02 ,  H01L23/48 ,  H01L23/482 ,  H01L27/085 ,  H01L29/778 ,  H01L27/06 ,  H02M3/335

CPC classification number: H01L23/481 ,  H01L23/4824 ,  H01L27/085 ,  H01L29/7786 ,  H01L27/0605 ,  H02M3/33569

Abstract: An integrated semiconductor device includes an Si substrate, and a high-side transistor and a low-side transistor which configure a half-bridge. A source electrode of a unit transistor configuring the high-side transistor and a drain electrode of a unit transistor configuring the low-side transistor are integrated as a common electrode.

公开(公告)号：US10475802B2

公开(公告)日：2019-11-12

申请号：US15812525

申请日：2017-11-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Ayanori Ikoshi ,  Manabu Yanagihara

IPC: H01L27/11517 ,  H01L29/423 ,  H01L29/778 ,  H01L29/06 ,  H01L29/417 ,  H01L29/20

Abstract: A semiconductor device includes: a substrate; a first nitride semiconductor layer and a second nitride semiconductor layer having a band gap wider than a band gap of the first nitride semiconductor layer; a first active region which includes a source electrode, a drain electrode, and a gate electrode, and has a first carrier layer located in the first nitride semiconductor layer; and a second active region which is on an extension of a long-side direction of the drain electrode and has a second carrier layer located in the first nitride semiconductor layer via an element isolation region, and a potential of the second carrier layer is substantially same as a potential of a source extraction electrode in the second active region or is an intermediate potential between a potential of a gate extraction electrode and the potential of the source extraction electrode opposite a short side of the drain electrode.

公开(公告)号：US12284825B2

公开(公告)日：2025-04-22

申请号：US17770010

申请日：2020-10-29

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Manabu Yanagihara ,  Takahiro Sato ,  Hiroto Yamagiwa ,  Masahiro Hikita

IPC: H10D84/01 ,  H10D8/60 ,  H10D30/47 ,  H10D62/85

Abstract: The semiconductor device includes: a semiconductor substrate; a first transistor disposed above the semiconductor substrate and including a first source electrode, a first gate region, and a first drain electrode; and a second transistor disposed above the semiconductor substrate and including a second source electrode, a second gate region, and a second drain electrode. The first source electrode, the second gate region, and the second source electrode are substantially at an identical potential. The first drain electrode and the second drain electrode are substantially at an identical potential.

公开(公告)号：US09818835B2

公开(公告)日：2017-11-14

申请号：US15234775

申请日：2016-08-11

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Saichirou Kaneko ,  Hiroto Yamagiwa ,  Ayanori Ikoshi ,  Masayuki Kuroda ,  Manabu Yanagihara ,  Kenichiro Tanaka ,  Tetsuyuki Fukushima

IPC: H01L29/47 ,  H01L21/28 ,  H01L29/872 ,  H01L29/778 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/475 ,  H01L21/28 ,  H01L29/0619 ,  H01L29/1029 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/872

Abstract: In a semiconductor device in the present disclosure, a first nitride semiconductor layer has a two-dimensional electron gas channel in a vicinity of an interface with a second nitride semiconductor layer. In plan view, an electrode portion is provided between a first electrode and a second electrode with a space between the first electrode and the second electrode, and a space between the second electrode and the electrode portion is smaller than the space between the first electrode and the electrode portion. An energy barrier is provided in a junction surface between the electrode portion and the second nitride semiconductor layer, the energy barrier indicating a rectifying action in a forward direction from the electrode portion to the second nitride semiconductor layer, and a bandgap of the second nitride semiconductor layer is wider than a bandgap of the first nitride semiconductor layer.

公开(公告)号：US09680053B2

公开(公告)日：2017-06-13

申请号：US14934244

申请日：2015-11-06

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Masayuki Kuroda ,  Manabu Yanagihara ,  Shinichi Oki

IPC: H01L33/06 ,  H01L33/00 ,  H01L29/778 ,  H01L33/32 ,  H01L29/20 ,  H01L25/16 ,  H01L27/15 ,  H01L33/18 ,  H01L29/872 ,  H01L33/36

CPC classification number: H01L33/06 ,  H01L25/167 ,  H01L27/15 ,  H01L29/2003 ,  H01L29/7786 ,  H01L29/872 ,  H01L33/0008 ,  H01L33/0025 ,  H01L33/0033 ,  H01L33/0041 ,  H01L33/18 ,  H01L33/32 ,  H01L33/36 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A nitride semiconductor device includes a transistor having a semiconductor stacked body formed on a substrate, and a pn light-emitting body formed on the semiconductor stacked body. The semiconductor stacked body includes a first nitride semiconductor layer, and a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a bandgap wider than that of the first nitride semiconductor layer. The transistor includes: the semiconductor stacked body; a source electrode and a drain electrode formed away from each other on the semiconductor stacked body; and a gate electrode provided between the source electrode and the drain electrode and formed away from the source electrode and the drain electrode. The pn light-emitting body includes a p-type nitride semiconductor layer and an n-type nitride semiconductor layer to emit a light beam having an energy value higher than an electron trapping level existing in the semiconductor stacked body, in which the p-type nitride semiconductor layer of the pn light-emitting body is electrically connected to the gate electrode, and functions as a gate of the transistor.

公开(公告)号：US12255127B2

公开(公告)日：2025-03-18

申请号：US17190261

申请日：2021-03-02

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Hidekazu Nakamura ,  Manabu Yanagihara ,  Tomohiko Nakamura ,  Yusuke Katagiri ,  Katsumi Otani ,  Takeshi Kawabata

IPC: H01L23/495 ,  H01L21/52 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/07 ,  H01L25/18 ,  H01L29/20

Abstract: A semiconductor device that is a surface mount-type device includes a nitride semiconductor chip including a silicon substrate having a first thermal expansion coefficient and an InxGayAl1-x-yN layer in contact with a surface of the silicon substrate, where 0≤x≤1, 0≤y≤1, 0≤x+y≤1; and a die pad including Cu and having a second thermal expansion coefficient that is greater than the first thermal expansion coefficient. A thickness of the nitride semiconductor chip is at least 0.2 mm, length L of the nitride semiconductor chip is at least 3.12 mm, and thickness tm of the die pad and length L of the nitride semiconductor chip satisfy tm≥2.00×10−3×L2+0.173, tm being a thickness in mm and L being a length in mm.

公开(公告)号：US11189549B2

公开(公告)日：2021-11-30

申请号：US16363828

申请日：2019-03-25

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Hidekazu Nakamura ,  Manabu Yanagihara ,  Tomohiko Nakamura ,  Yusuke Katagiri ,  Katsumi Otani ,  Takeshi Kawabata

IPC: H01L23/495 ,  H01L29/20 ,  H01L23/00 ,  H01L25/07 ,  H01L25/18 ,  H01L21/52 ,  H01L23/48 ,  H01L23/31

Abstract: A semiconductor device that is a surface mount-type device includes a nitride semiconductor chip including a silicon substrate having a first thermal expansion coefficient and an InxGayAl1-x-yN layer in contact with a surface of the silicon substrate, where 0≤x≤1, 0≤y≤1, 0≤x+y≤1; and a die pad including Cu and having a second thermal expansion coefficient that is greater than the first thermal expansion coefficient. A thickness of the nitride semiconductor chip is at least 0.2 mm, length L of the nitride semiconductor chip is at least 3.12 mm, and thickness tm of the die pad and length L of the nitride semiconductor chip satisfy tm≥2.00×10−3×L2+0.173, tm being a thickness in mm and L being a length in mm.

公开(公告)号：US11152499B2

公开(公告)日：2021-10-19

申请号：US16575075

申请日：2019-09-18

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hideyuki Okita ,  Manabu Yanagihara ,  Takahiro Sato ,  Masahiro Hikita

IPC: H01L29/205 ,  H01L29/778 ,  H01L29/417 ,  H01L29/36 ,  H01L29/207 ,  H01L29/66 ,  H01L21/02 ,  H01L29/43 ,  H01L29/20 ,  H01L21/306 ,  H01L21/223 ,  H01L21/027

Abstract: A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer; a second nitride semiconductor layer having a greater band gap than the first nitride semiconductor layer; a source electrode and a drain electrode on the second nitride semiconductor layer apart from each other; a third nitride semiconductor layer, between the source electrode and the drain electrode, containing a p-type first impurity and serving as a gate; and a fourth nitride semiconductor layer, between the third nitride semiconductor layer and the drain electrode, containing a p-type second impurity, wherein the average carrier concentration of the fourth nitride semiconductor layer is lower than the average carrier concentration of the third nitride semiconductor layer.

公开(公告)号：US10090220B2

公开(公告)日：2018-10-02

申请号：US15427629

申请日：2017-02-08

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Ayanori Ikoshi ,  Masahiro Hikita ,  Keiichi Matsunaga ,  Takahiro Sato ,  Manabu Yanagihara

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/00 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417

Abstract: A semiconductor device includes a substrate; a semiconductor layer; a first protective film; a first adhesive layer disposed on the first protective film; an electrode pad disposed on the first protective film; a second protective film disposed to cover and be in contact with the electrode pad and the first adhesive layer; and a first opening formed in part of the second protective film such that the upper surface of the electrode pad is exposed, wherein in a plan view, the first adhesive layer includes a first projection projecting from the electrode pad radially in a direction of the periphery of the electrode pad and continuously surrounding the periphery of the electrode pad; and the second protective film is continuously to cover and contact part of the upper and side surfaces of the electrode pad, the upper and side surfaces of first projection, and the first protective film.

公开(公告)号：US09923069B1

公开(公告)日：2018-03-20

申请号：US15445358

申请日：2017-02-28

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Ryusuke Kanomata ,  Ayanori Ikoshi ,  Hiroto Yamagiwa ,  Saichirou Kaneko ,  Manabu Yanagihara

IPC: H01L29/739 ,  H01L29/417 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  G01R31/26

CPC classification number: H01L29/41758 ,  G01R31/2642 ,  H01L29/0619 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/8613 ,  H01L29/872

Abstract: A nitride semiconductor device includes: a stacked structure portion having an active region; first and second main electrodes extending in a first direction; and a lead-out line (second lead-out line) electrically connected to the second main electrode and extends to one side in the first direction. The first main electrode has a first tip at an end which is on the side to which the lead-out line extends. The second main electrode has a second tip at an end which is on the side to which the lead-out line extends, and has, at a second tip-side in the first direction, a tapered portion having a width in a second direction which decreases with decreasing distance to the second tip. The lead-out line has a region projecting in the second direction from the tapered portion, and the first tip does not project further in the first direction than the second tip.