公开(公告)号：US09837496B2

公开(公告)日：2017-12-05

申请号：US14930628

申请日：2015-11-02

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yusuke Kinoshita ,  Satoshi Tamura ,  Tetsuzo Ueda

IPC: H01L29/06 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778 ,  H01L29/808 ,  H01L29/43 ,  H01L29/10 ,  H01L29/20 ,  H01L29/201

CPC classification number: H01L29/205 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/66916 ,  H01L29/66924 ,  H01L29/7786 ,  H01L29/8086

Abstract: A semiconductor device includes: a channel layer which is made of InpAlqGa1-p-qN (0≦p+q≦1, 0≦p, and 0≦q); a barrier layer which is formed on the channel layer and is made of InrAlsGa1-r-sN (0≦r+s≦1, 0≦r) having a bandgap larger than that of the channel layer; a diffusion suppression layer which is selectively formed on the barrier layer and is made of IntAluGa1-t-uN (0≦t+u≦1, 0≦t, and s>u); a p-type conductive layer which is formed on the diffusion suppression layer and is made of InxAlyGa1-x-yN (0≦x+y≦1, 0≦x, and 0≦y) having p-type conductivity; and a gate electrode which is formed on the p-type conductive layer.

公开(公告)号：US10128363B2

公开(公告)日：2018-11-13

申请号：US14736665

申请日：2015-06-11

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Satoshi Nakazawa ,  Tetsuzo Ueda

IPC: H01L29/00 ,  H01L29/778 ,  H01L29/66 ,  H01L29/423 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/51 ,  H01L29/10

Abstract: Provided is a field-effect transistor (FET) that achieves compatibility between a higher current density and lower contact resistance and exhibits excellent properties, and a method for producing the FET. The FET includes: a channel layer above a substrate; an InAlN layer above the channel layer; an InxAlyGa1-(x+y)N layer on the InAlN layer, where 0

公开(公告)号：US10453776B2

公开(公告)日：2019-10-22

申请号：US15196153

申请日：2016-06-29

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Ryosuke Usui ,  Tetsuzo Ueda

IPC: H01L23/10 ,  H01L23/34 ,  H01L23/473 ,  H01L23/495 ,  H02M7/48 ,  H01L23/053 ,  H01L23/528 ,  H01L49/02 ,  H05K7/20

Abstract: A semiconductor device includes a semiconductor module including a semiconductor element, a passive element, a cooling member, a first conductive member and a second conductive member. The cooling member is disposed between the semiconductor module and the passive element. And a first conductive member and a second conductive member electrically connect the semiconductor module and the passive element. Furthermore, two or more aspects of at least one of the first conductive member and the second conductive member face the cooling member.

公开(公告)号：US09666664B2

公开(公告)日：2017-05-30

申请号：US14663140

申请日：2015-03-19

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Ryo Kajitani ,  Tetsuzo Ueda ,  Yoshiharu Anda ,  Naohiro Tsurumi ,  Satoshi Nakazawa

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/0611 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/404 ,  H01L29/51 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/78

Abstract: An object is to achieve an increase in gain by reducing a current collapse, and reducing Cgd and Rg. A semiconductor device according to the present invention includes a substrate; a first semiconductor layer disposed on the substrate and made of a Group III nitride semiconductor; a second semiconductor layer disposed on the first semiconductor layer and made of a Group III nitride semiconductor; a gate electrode, a source electrode, and a drain electrode disposed on the second semiconductor layer; a first field plate electrode disposed on the second semiconductor layer; and a second field plate electrode disposed on the first field plate electrode, in which the first field plate electrode and the second field plate electrode are disposed between the gate electrode and the drain electrode.

公开(公告)号：US09401403B2

公开(公告)日：2016-07-26

申请号：US14636163

申请日：2015-03-02

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidekazu Umeda ,  Masahiro Ishida ,  Tetsuzo Ueda ,  Daisuke Ueda

IPC: H01L21/02 ,  H01L21/762 ,  H01L29/205 ,  H01L29/778 ,  H01L29/86 ,  H01L29/15 ,  H01L29/20 ,  H01L29/36

CPC classification number: H01L29/205 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L29/1066 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/7786 ,  H01L29/86

Abstract: A nitride semiconductor structure of the present disclosure comprises a semiconductor substrate, and a layer formed over the semiconductor substrate and comprising plural nitride semiconductor layers. The semiconductor substrate has, from a side thereof near the layer comprising the plural nitride semiconductor layers, a surface region and an internal region in this order. The surface region has a resistivity of 0.1 Ωcm or more, and the internal region has a resistivity of 1000 Ωcm or more.

Abstract translation: 本公开的氮化物半导体结构包括半导体衬底和形成在半导体衬底上并包括多个氮化物半导体层的层。 半导体衬底从其包括多个氮化物半导体层的层的一侧开始依次具有表面区域和内部区域。 表面区域的电阻率为0.1Ωcm以上，内部区域的电阻率为1000Ωcm以上。

公开(公告)号：US09595606B2

公开(公告)日：2017-03-14

申请号：US14790064

申请日：2015-07-02

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Kenichiro Tanaka ,  Shinichi Kohda ,  Masahiro Ishida ,  Tetsuzo Ueda

IPC: H01L29/778 ,  H01L29/36 ,  H01L29/207 ,  H01L29/06 ,  H01L29/205 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L29/0684 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/36 ,  H01L29/7786

Abstract: A field-effect transistor includes a codoped layer made of AlxGa1-xN (0≦x≦1) and formed on a p-type Si substrate, a GaN layer formed on the codoped layer, and an AlGaN layer formed on the GaN layer. The codoped layer contains C and Si as impurity elements. The impurity concentration of C in the codoped layer is equal to or higher than 5×1017/cm3. The impurity concentration of Si in the codoped layer is lower than the impurity concentration of C. The impurity concentration of C in the GaN layer is equal to or lower than 1×1017/cm3. The thickness of the GaN layer is equal to or greater than 0.75 μm.

Abstract translation: 场效应晶体管包括由Al x Ga 1-x N（0≤x≤1）构成并形成在p型Si衬底上的共掺层，在共掺层上形成的GaN层和形成在GaN层上的AlGaN层。 共掺层含有C和Si作为杂质元素。 共掺层中的C的杂质浓度等于或高于5×1017 / cm3。 共掺层中Si的杂质浓度低于C的杂质浓度.Ca层中的C的杂质浓度等于或低于1×1017 / cm3。 GaN层的厚度等于或大于0.75μm。

公开(公告)号：US09484342B2

公开(公告)日：2016-11-01

申请号：US14938803

申请日：2015-11-11

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hiroyuki Handa ,  Hidekazu Umeda ,  Satoshi Tamura ,  Tetsuzo Ueda

IPC: H01L27/06 ,  H01L23/535 ,  H01L29/778 ,  H01L29/861 ,  H01L29/872 ,  H01L29/205 ,  H01L27/095 ,  H01L29/417 ,  H01L29/20 ,  H01L29/10

CPC classification number: H01L27/0629 ,  H01L23/535 ,  H01L27/0605 ,  H01L27/0635 ,  H01L27/095 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/417 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/861 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor apparatus includes a substrate; a nitride semiconductor layer formed on the substrate; a transistor formed on the nitride semiconductor layer, and including a source electrode, a gate electrode, and a drain electrode disposed in this order; and a diode formed on the nitride semiconductor layer, and including an anode electrode and a cathode electrode disposed in this order. The semiconductor apparatus has a transistor/diode pair in which the source electrode, the gate electrode, the drain electrode, the anode electrode, and the cathode electrode are sequentially disposed in this order, and the drain electrode of the transistor and the anode electrode of the diode are connected by a drain/anode common electrode wiring and serve as a common electrode.

Abstract translation: 一种半导体装置，包括：基板; 形成在所述基板上的氮化物半导体层; 形成在所述氮化物半导体层上的晶体管，并且包括依次设置的源电极，栅极电极和漏极电极; 以及形成在氮化物半导体层上的二极管，并且包括依次设置的阳极电极和阴极电极。 半导体装置具有晶体管/二极管对，其中源电极，栅电极，漏电极，阳极电极和阴极电极依次依次设置，晶体管的漏电极和阳极电极 二极管通过漏极/阳极公共电极布线连接并用作公共电极。

公开(公告)号：US09406668B2

公开(公告)日：2016-08-02

申请号：US14779104

申请日：2014-02-25

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shuichi Nagai ,  Daisuke Ueda ,  Tatsuo Morita ,  Tetsuzo Ueda

IPC: H01L29/778 ,  H01L27/06 ,  H01L29/20 ,  H01L27/02 ,  H03K17/082 ,  H01L27/07

CPC classification number: H01L27/0605 ,  H01L27/0207 ,  H01L27/0248 ,  H01L27/0629 ,  H01L27/0727 ,  H01L27/0738 ,  H01L29/2003 ,  H01L29/778 ,  H03K17/0822

Abstract: A power semiconductor element includes: a main transistor including a first gate electrode, a first drain electrode, and a first source electrode; a sensor transistor including a second gate electrode, a second drain electrode, and a second source electrode; and a gate switch transistor including a third gate electrode, and a third drain electrode, a third source electrode. The first gate electrode, the second gate electrode, and the third drain electrode are connected, the first drain electrode and the second drain electrode are connected, the first source electrode and the second source electrode are connected via a sensor resistor, the first source electrode and the third source electrode are connected, the second source electrode and the third gate electrode are connected via a switch resistor, and the main transistor, the sensor transistor, and the gate switch transistor are formed with a nitride semiconductor.

Abstract translation: 功率半导体元件包括：主晶体管，包括第一栅电极，第一漏电极和第一源电极; 传感器晶体管，包括第二栅极电极，第二漏极电极和第二源极电极; 以及栅极开关晶体管，其包括第三栅极电极和第三漏极电极，第三源极电极。 第一栅电极，第二栅极电极和第三漏电极连接，第一漏电极和第二漏极连接，第一源电极和第二源极通过传感器电阻连接，第一源电极 并且第三源电极连接，第二源电极和第三栅极经由开关电阻器连接，并且主晶体管，传感器晶体管和栅极开关晶体管由氮化物半导体形成。