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    Forming of the periphery of a schottky diode with MOS trenches
    1.
    发明授权
    Forming of the periphery of a schottky diode with MOS trenches 有权
    形成具有MOS沟槽的肖特基二极管的外围

    公开(公告)号：US07820494B2

    公开(公告)日：2010-10-26

    申请号：US11713543

    申请日：2007-03-02

    Applicant: Patrick Poveda

    Inventor： Patrick Poveda

    IPC: H01L21/338

    CPC classification number: H01L29/402 ,  H01L29/407 ,  H01L29/66143 ,  H01L29/806 ,  H01L29/872 ,  H01L29/8725

    Abstract: A method for forming a component of TMBS type having its periphery formed of a trench with insulated walls filled with a conductor, including the steps of depositing on a semiconductor substrate a thick layer of a first insulating material and a thin layer of a second material; simultaneously digging a peripheral trench and the trenches of the component; isotropically etching the first material so that a cap overhanging a recess remains; forming a thin insulating layer; and filling the trenches and said recess with a conductive material.

    Abstract translation: 一种用于形成其外围由填充有导体的绝缘壁形成沟槽的TMBS型的部件的方法，包括以下步骤：在半导体衬底上沉积厚层的第一绝缘材料和第二材料的薄层; 同时挖掘周边沟槽和部件的沟槽; 各向同性蚀刻第一材料，使得悬挂在凹部上的盖保留; 形成薄的绝缘层; 并用导电材料填充沟槽和凹槽。

    Forming of the periphery of a schottky diode with MOS trenches
    2.
    发明申请
    Forming of the periphery of a schottky diode with MOS trenches 有权
    形成具有MOS沟槽的肖特基二极管的外围

    公开(公告)号：US20070222018A1

    公开(公告)日：2007-09-27

    申请号：US11713543

    申请日：2007-03-02

    Applicant: Patrick Poveda

    Inventor： Patrick Poveda

    IPC: H01L27/00

    CPC classification number: H01L29/402 ,  H01L29/407 ,  H01L29/66143 ,  H01L29/806 ,  H01L29/872 ,  H01L29/8725

    Abstract: A method for forming a component of TMBS type having its periphery formed of a trench with insulated walls filled with a conductor, including the steps of depositing on a semiconductor substrate a thick layer of a first insulating material and a thin layer of a second material; simultaneously digging a peripheral trench and the trenches of the component; isotropically etching the first material so that a cap overhanging a recess remains; forming a thin insulating layer; and filling the trenches and said recess with a conductive material.

    Abstract translation: 一种用于形成其外围由填充有导体的绝缘壁形成沟槽的TMBS型的部件的方法，包括以下步骤：在半导体衬底上沉积厚层的第一绝缘材料和第二材料的薄层; 同时挖掘周边沟槽和部件的沟槽; 各向同性蚀刻第一材料，使得悬挂在凹部上的盖保留; 形成薄的绝缘层; 并用导电材料填充沟槽和凹槽。

    Low-capacity vertical diode
    3.
    发明授权
    Low-capacity vertical diode 有权
    低容量立式二极管

    公开(公告)号：US06924546B2

    公开(公告)日：2005-08-02

    申请号：US10489153

    申请日：2002-09-10

    Applicant: Emmanuel Collard ,  Patrick Poveda

    Inventor： Emmanuel Collard ,  Patrick Poveda

    IPC: H01L29/861 ,  H01L29/868 ,  H01L31/105

    CPC classification number: H01L29/868 ,  H01L29/8613

    Abstract: The invention concerns a low-capacity vertical diode designed to be mounted by a front surface made in a semiconductor substrate (1), comprising a first zone projecting relative to the surface of the substrate including at least a semiconductor layer (3) doped with a type of conductivity opposite to that of the substrate, the upper surface of the semiconductor layer bearing a first solder bump (23). The diode comprises a second zone including on the substrate a thick strip conductor (16) bearing at least second solder bumps (24), said first and second solder bumps defining a plane parallel to the substrate plane.

    Abstract translation: 本发明涉及一种设计成由半导体衬底（1）制成的前表面安装的低容量垂直二极管，包括相对于衬底的表面突出的第一区域，该第一区域包括至少掺杂有半导体衬底的半导体层（3） 类型的导电性与衬底的导电性相反，半导体层的上表面具有第一焊料凸点（23）。 所述二极管包括第二区域，所述第二区域在所述衬底上具有承载至少第二焊料凸块（24）的厚条状导体（16），所述第一和第二焊料凸块限定平行于所述衬底平面的平面。

    Antenna switch module
    4.
    发明授权
    Antenna switch module 有权
    天线开关模块

    公开(公告)号：US07589602B2

    公开(公告)日：2009-09-15

    申请号：US11490740

    申请日：2006-07-21

    Applicant: Patrick Poveda ,  Francois Dupont

    Inventor： Patrick Poveda ,  Francois Dupont

    IPC: H01P1/10 ,  H01P5/12 ,  H04B1/44 ,  H04B1/46

    CPC classification number: H04B1/005 ,  H04B1/406 ,  H04B1/48

    Abstract: An antenna switch module between several radio-frequency transmit and/or receive paths including, between a common terminal on the antenna side and an access capacitor specific to each path, at least one diode, the number of diodes directly connected to the common terminal being odd and the number of diodes having their cathode on the common terminal side being equal, with a difference of one, to the number of diodes having their anode on the common terminal side.

    Abstract translation: 在几个射频发射和/或接收路径之间的天线切换模块，包括在天线侧的公共终端和每个路径专用的接入电容器之间，至少一个二极管，直接连接到公共端子的二极管的数量为 奇数，在公共端子侧具有阴极的二极管的数量与公共端子侧的具有阳极的二极管的数量相差1。

    Thermally-controlled actuator device
    5.
    发明申请
    Thermally-controlled actuator device 审中-公开
    热控致动器装置

    公开(公告)号：US20060037998A1

    公开(公告)日：2006-02-23

    申请号：US11256508

    申请日：2005-10-21

    Applicant: Stephane Crabol ,  Guy Valembois ,  Patrick Poveda

    Inventor： Stephane Crabol ,  Guy Valembois ,  Patrick Poveda

    IPC: B23K31/02

    CPC classification number: B64G1/645 ,  B64G1/222

    Abstract: The present invention relates to a thermally-controlled actuator device of the type comprising a body, a part held stationary relative to the body by a low-melting point connection material, e.g. brazing or equivalent means, and a mass of exothermic material suitable for acting on command to give off intense heat energy suitable for melting the connection material so as to release the part relative to the body, wherein the exothermic material is housed in a chamber that is subdivided into a plurality of compartments suitable for confining said material in close thermal contact with the wall of the chamber.

    Abstract translation: 本发明涉及一种热控致动器装置，其类型包括主体，通过低熔点连接材料相对于主体保持固定的部分，例如， 钎焊或等效装置，以及大量放热材料，其适于作用于发出适于熔化连接材料的强热能，以便相对于主体释放该部件，其中放热材料容纳在室 细分成多个适合于限制所述材料与室的壁紧密热接触的隔室。

    Low-capacity vertical diode
    6.
    发明申请
    Low-capacity vertical diode 有权
    低容量立式二极管

    公开(公告)号：US20050242363A1

    公开(公告)日：2005-11-03

    申请号：US11159991

    申请日：2005-06-23

    Applicant: Emmanuel Collard ,  Patrick Poveda

    Inventor： Emmanuel Collard ,  Patrick Poveda

    IPC: H01L29/861 ,  H01L29/868 ,  H01L29/22

    CPC classification number: H01L29/868 ,  H01L29/8613

    Abstract: A vertical diode of low capacitance formed in a front surface of a semiconductor substrate, including a first area protruding from the substrate surface including at least one doped semiconductor layer of a conductivity type opposite to that of the substrate, the upper surface of the semiconductor layer supporting a first welding ball. The diode includes a second area including on the substrate a thick conductive track supporting at least two second welding balls, said first and second welding balls defining a plane parallel to the substrate plane.

    Abstract translation: 一种低电容的垂直二极管，其形成在半导体衬底的前表面中，包括从衬底表面突出的第一区域，该第一区域包括至少一个与衬底相反的导电类型的掺杂半导体层，半导体层的上表面 支持第一焊球。 二极管包括第二区域，该第二区域包括在基板上的支撑至少两个第二焊球的厚导电轨道，所述第一焊球和第二焊球限定平行于衬底平面的平面。

    Integrated coupler
    7.
    发明申请
    Integrated coupler 有权
    集成耦合器

    公开(公告)号：US20050073373A1

    公开(公告)日：2005-04-07

    申请号：US10949941

    申请日：2004-09-24

    Applicant: Francois Dupont ,  Patrick Poveda

    Inventor： Francois Dupont ,  Patrick Poveda

    IPC: H01L21/822 ,  H01L27/04 ,  H03H7/48 ,  H01P5/12

    CPC classification number: H03H7/487

    Abstract: A non-directional coupler including a semiconductor junction in series with a capacitor, the semiconductor junction being formed so that the threshold frequency short of which it behaves as a rectifier is smaller than the coupler's operating frequency.

    Abstract translation: 包括与电容器串联的半导体结的非定向耦合器，形成半导体结，使得其作为整流器行为的阈值频率小于耦合器的工作频率。

    INSULATED WELL WITH A LOW STRAY CAPACITANCE FOR ELECTRONIC COMPONENTS
    9.
    发明申请
    INSULATED WELL WITH A LOW STRAY CAPACITANCE FOR ELECTRONIC COMPONENTS 审中-公开
    绝缘良好，电子元件的低电阻电容

    公开(公告)号：US20100187650A1

    公开(公告)日：2010-07-29

    申请号：US12690717

    申请日：2010-01-20

    Applicant: Patrick Poveda ,  Benjamin Morillon ,  Erwan Bruno

    Inventor： Patrick Poveda ,  Benjamin Morillon ,  Erwan Bruno

    IPC: H01L29/06 ,  H01L21/762

    CPC classification number: H01L21/76264 ,  H01L27/0814

    Abstract: A structure including at least one electronic component formed in a semiconductor stack comprising a heavily-doped buried silicon layer of a first conductivity type extending on a lightly-doped silicon substrate of a second conductivity type and a vertical insulating trench surrounding the component. The trench penetrates, into the silicon substrate, under the silicon layer, down to a depth greater than the thickness of the space charge region in the silicon substrate.

    Abstract translation: 包括形成在半导体堆叠中的至少一个电子部件的结构，包括在第二导电类型的轻掺杂硅衬底上延伸的第一导电类型的重掺杂掩埋硅层和围绕该部件的垂直绝缘沟槽。 沟槽在硅层之下穿入硅衬底，直到深度大于硅衬底中的空间电荷区的厚度。

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