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公开(公告)号：US20100220536A1
公开(公告)日：2010-09-02
申请号：US12394804
申请日：2009-02-27
申请人： Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Kyu-hyoun Kim , Kenneth L. Wright
发明人： Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Kyu-hyoun Kim , Kenneth L. Wright
CPC分类号： G11C7/22 , G06F13/1689 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1066 , G11C7/222 , G11C8/12 , Y02D10/14
摘要： A memory device including a memory array storing data, a variable delay controller, a passive variable delay circuit and an output driver. The variable delay controller periodically receives delay commands from a first source external to the memory device during operation of the memory device, and outputs delay instruction bits responsive to the received delay commands. The passive variable delay circuit receives a clock from a second source external to the memory device, receives the delay instruction bits from the variable delay controller, generates a delayed clock having a time relation to the received clock as determined by the delay instruction bits, and outputting the delayed clock. The output driver receives the data from the memory array and the delayed clock, and outputs the data at a time responsive to the delayed clock.
摘要翻译： 一种包括存储数据的存储器阵列，可变延迟控制器，无源可变延迟电路和输出驱动器的存储器件。 可变延迟控制器在存储器件的操作期间周期性地从存储器件外部的第一源接收延迟命令，并且响应于接收的延迟命令而输出延迟指令位。 无源可变延迟电路从存储器件外部的第二源接收时钟，从可变延迟控制器接收延迟指令位，产生与由延迟指令位确定的接收时钟具有时间关系的延迟时钟，以及 输出延迟时钟。 输出驱动器从存储器阵列和延迟时钟接收数据，并且响应于延迟的时钟一次输出数据。
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2.发明授权公开(公告)号：US07948817B2
公开(公告)日：2011-05-24
申请号：US12394804
申请日：2009-02-27
申请人： Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Kyu-hyoun Kim , Kenneth L. Wright
发明人： Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Kyu-hyoun Kim , Kenneth L. Wright
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G06F13/1689 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1066 , G11C7/222 , G11C8/12 , Y02D10/14
摘要： A memory device including a memory array storing data, a variable delay controller, a passive variable delay circuit and an output driver. The variable delay controller periodically receives delay commands from a first source external to the memory device during operation of the memory device, and outputs delay instruction bits responsive to the received delay commands. The passive variable delay circuit receives a clock from a second source external to the memory device, receives the delay instruction bits from the variable delay controller, generates a delayed clock having a time relation to the received clock as determined by the delay instruction bits, and outputting the delayed clock. The output driver receives the data from the memory array and the delayed clock, and outputs the data at a time responsive to the delayed clock.
摘要翻译： 一种包括存储数据的存储器阵列，可变延迟控制器，无源可变延迟电路和输出驱动器的存储器件。 可变延迟控制器在存储器件的操作期间周期性地从存储器件外部的第一源接收延迟命令，并且响应于接收的延迟命令而输出延迟指令位。 无源可变延迟电路从存储器件外部的第二源接收时钟，从可变延迟控制器接收延迟指令位，产生与由延迟指令位确定的接收时钟具有时间关系的延迟时钟，以及 输出延迟时钟。 输出驱动器从存储器阵列和延迟时钟接收数据，并且响应于延迟的时钟一次输出数据。
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公开(公告)号：US20100138684A1
公开(公告)日：2010-06-03
申请号：US12326126
申请日：2008-12-02
申请人： Kyu-hyoun Kim , Paul W. Coteus , Alan Gara , Vipin Patel , Kenneth L. Wright
发明人： Kyu-hyoun Kim , Paul W. Coteus , Alan Gara , Vipin Patel , Kenneth L. Wright
CPC分类号： G06F1/324 , G06F1/3225 , G06F1/3275 , G06F1/3296 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： A memory controller, memory device, and method for dynamic supply voltage scaling in a memory system are provided. The method includes receiving a request for a supply voltage change at the memory controller in the memory system, the supply voltage powering the memory device. The method further includes waiting for any current access of the memory device to complete, and disabling a clock between the memory controller and the memory device. The method also includes changing the supply voltage responsive to the request, and enabling the clock.
摘要翻译： 提供了一种存储器控制器，存储器件和用于存储器系统中的动态电源电压缩放的方法。 该方法包括在存储器系统中的存储器控制器处接收对电源电压变化的请求，为存储器件提供电源电压。 该方法还包括等待存储器设备的任何当前访问以完成存储器控制器和存储器设备之间的时钟的禁用。 该方法还包括响应于该请求改变电源电压，并启用时钟。
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4.发明申请SYSTEM AND METHOD FOR PROVIDING A NON-POWER-OF-TWO BURST LENGTH IN A MEMORY SYSTEM 有权用于在存储器系统中提供非功率的两个BURST长度的系统和方法公开(公告)号：US20090251988A1
公开(公告)日：2009-10-08
申请号：US12061045
申请日：2008-04-02
IPC分类号： G11C8/00
CPC分类号： G11C5/00 , G11C7/1018
摘要： A memory system, memory interface device and method for a non-power-of-two burst length are provided. The memory system includes a plurality of memory devices with non-power-of-two burst length logic and a memory interface device including non-power-of-two burst length generation logic. The non-power-of-two burst length generation logic extends a burst length from a power-of-two value to insert an error-detecting code in a burst on data lines between the memory interface device and the plurality of memory devices.
摘要翻译： 提供了一种用于非二次突发长度的存储器系统，存储器接口装置和方法。 存储器系统包括具有非二次突发长度逻辑的多个存储器件和包括非二次突发长度生成逻辑的存储器接口器件。 非功率二突发长度生成逻辑从两个功率值扩展突发长度，以将错误检测码插入到存储器接口设备和多个存储器件之间的数据线上的突发中。
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5.发明授权System and method for providing a non-power-of-two burst length in a memory system 有权在存储器系统中提供非二次突发长度的系统和方法公开(公告)号：US08023358B2
公开(公告)日：2011-09-20
申请号：US12061045
申请日：2008-04-02
IPC分类号： G11C8/00
CPC分类号： G11C5/00 , G11C7/1018
摘要： A memory system, memory interface device and method for a non-power-of-two burst length are provided. The memory system includes a plurality of memory devices with non-power-of-two burst length logic and a memory interface device including non-power-of-two burst length generation logic. The non-power-of-two burst length generation logic extends a burst length from a power-of-two value to insert an error-detecting code in a burst on data lines between the memory interface device and the plurality of memory devices.
摘要翻译： 提供了一种用于非二次突发长度的存储器系统，存储器接口装置和方法。 存储器系统包括具有非二次突发长度逻辑的多个存储器件和包括非二次突发长度生成逻辑的存储器接口器件。 非功率二突发长度生成逻辑从两个功率值扩展突发长度，以将错误检测码插入到存储器接口设备和多个存储器件之间的数据线上的突发中。
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公开(公告)号：US20130313705A1
公开(公告)日：2013-11-28
申请号：US13477371
申请日：2012-05-22
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L25/0657 , H01L23/481 , H01L23/498 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L2224/0401 , H01L2224/05009 , H01L2224/05027 , H01L2224/13014 , H01L2224/13021 , H01L2224/13025 , H01L2224/131 , H01L2224/14051 , H01L2224/1411 , H01L2224/1613 , H01L2224/16146 , H01L2224/17106 , H01L2224/73204 , H01L2225/06513 , H01L2225/06541 , H01L2924/00012 , H01L2924/00014 , H01L2924/014
摘要： A method and structures are provided for implementing decoupling capacitors within a DRAM TSV stack. A DRAM is formed with a plurality of TSVs extending completely through the substrate and filled with a conducting material. A layer of glass is grown on both the top and bottom of the DRAM providing an insulator. A layer of metal is grown on each glass layer providing a conductor. The metal and glass layers are etched through to TSVs with a gap provided around the perimeter of via pads. A respective solder ball is formed on the TSVs to connect to another DRAM chip in the DRAM TSV stack. The metal layers are connected to at least one TSV by one respective solder ball and are connected to a voltage source and a dielectric is inserted between the metal layers in the DRAM TSV stack to complete the decoupling capacitor.
摘要翻译： 提供了一种用于在DRAM TSV堆栈内实现去耦电容器的方法和结构。 形成有多个完全延伸穿过衬底并填充有导电材料的TSV的DRAM。 在提供绝缘体的DRAM的顶部和底部都生长玻璃层。 在提供导体的每个玻璃层上生长一层金属。 金属和玻璃层被蚀刻到具有围绕通孔焊盘的周边设置的间隙的TSV。 在TSV上形成相应的焊球以连接到DRAM TSV堆叠中的另一个DRAM芯片。 金属层通过一个相应的焊球连接到至少一个TSV，并且连接到电压源，并且电介质插入在DRAM TSV堆叠中的金属层之间以完成去耦电容器。
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公开(公告)号：US08697567B2
公开(公告)日：2014-04-15
申请号：US13477371
申请日：2012-05-22
IPC分类号： H01L21/768
CPC分类号： H01L25/0657 , H01L23/481 , H01L23/498 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L2224/0401 , H01L2224/05009 , H01L2224/05027 , H01L2224/13014 , H01L2224/13021 , H01L2224/13025 , H01L2224/131 , H01L2224/14051 , H01L2224/1411 , H01L2224/1613 , H01L2224/16146 , H01L2224/17106 , H01L2224/73204 , H01L2225/06513 , H01L2225/06541 , H01L2924/00012 , H01L2924/00014 , H01L2924/014
摘要： A method and structures are provided for implementing decoupling capacitors within a DRAM TSV stack. A DRAM is formed with a plurality of TSVs extending completely through the substrate and filled with a conducting material. A layer of glass is grown on both the top and bottom of the DRAM providing an insulator. A layer of metal is grown on each glass layer providing a conductor. The metal and glass layers are etched through to TSVs with a gap provided around the perimeter of via pads. A respective solder ball is formed on the TSVs to connect to another DRAM chip in the DRAM TSV stack. The metal layers are connected to at least one TSV by one respective solder ball and are connected to a voltage source and a dielectric is inserted between the metal layers in the DRAM TSV stack to complete the decoupling capacitor.
摘要翻译： 提供了一种用于在DRAM TSV堆栈内实现去耦电容器的方法和结构。 形成有多个完全延伸穿过衬底并填充有导电材料的TSV的DRAM。 在提供绝缘体的DRAM的顶部和底部都生长玻璃层。 在提供导体的每个玻璃层上生长一层金属。 金属和玻璃层被蚀刻到具有围绕通孔焊盘的周边设置的间隙的TSV。 在TSV上形成相应的焊球以连接到DRAM TSV堆叠中的另一个DRAM芯片。 金属层通过一个相应的焊球连接到至少一个TSV，并且连接到电压源，并且电介质插入在DRAM TSV堆叠中的金属层之间以完成去耦电容器。
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公开(公告)号：US20110075740A1
公开(公告)日：2011-03-31
申请号：US12568765
申请日：2009-09-29
IPC分类号： H04B3/00
CPC分类号： H04L25/0272 , Y02D30/30
摘要： An electronic system having a power efficient differential signal between a first and second electronic unit. A controller uses information, such as compliance with data transmission rate requirement and bit error rate (BER) versus a BER threshold to control power modes such that a minimal amount of power is required. Amplitude of transmission and single ended or differential transmission of data are examples of the power modes. The controller also factors in a failing phase in a differential signal in selecting a minimal power mode that satisfies the transmission rate requirement of the BER threshold.
摘要翻译： 一种在第一和第二电子单元之间具有功率有效的差分信号的电子系统。 控制器使用诸如符合数据传输速率要求和误码率（BER）与BER阈值的信息来控制功率模式，使得需要最小量的功率。 传输幅度和数据的单端或差分传输是功率模式的例子。 控制器还在选择满足BER阈值的传输速率要求的最小功率模式时，在差分信号中导致故障相位。
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公开(公告)号：US09325534B2
公开(公告)日：2016-04-26
申请号：US12568765
申请日：2009-09-29
CPC分类号： H04L25/0272 , Y02D30/30
摘要： An electronic system having a power efficient differential signal between a first and second electronic unit. A controller uses information, such as compliance with data transmission rate requirement and bit error rate (BER) versus a BER threshold to control power modes such that a minimal amount of power is required. Amplitude of transmission and single ended or differential transmission of data are examples of the power modes. The controller also factors in a failing phase in a differential signal in selecting a minimal power mode that satisfies the transmission rate requirement of the BER threshold.
摘要翻译： 一种在第一和第二电子单元之间具有功率有效的差分信号的电子系统。 控制器使用诸如符合数据传输速率要求和误码率（BER）与BER阈值的信息来控制功率模式，使得需要最小量的功率。 传输幅度和数据的单端或差分传输是功率模式的例子。 控制器还在选择满足BER阈值的传输速率要求的最小功率模式时，在差分信号中导致故障相位。
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公开(公告)号：US20110320881A1
公开(公告)日：2011-12-29
申请号：US12822508
申请日：2010-06-24
申请人： John S. Dodson , Frank D. Ferraiolo , Michele M. Franceschini , Kevin C. Gower , Lisa C. Gower , Ashish Jagmohan , Luis A. Lastras-Montano , Kenneth L. Wright
发明人： John S. Dodson , Frank D. Ferraiolo , Michele M. Franceschini , Kevin C. Gower , Lisa C. Gower , Ashish Jagmohan , Luis A. Lastras-Montano , Kenneth L. Wright
IPC分类号： G06F11/34
CPC分类号： G06F11/10 , G06F11/2005 , H04L1/0061 , H04L2001/0096
摘要： Isolation of faulty links in a transmission medium including a method that includes receiving an atomic data unit via a multi-link transmission medium that has a plurality of transmission links An error condition is detected and it is determined that the error condition is isolated to a single transmission link. It is determined if the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer. If the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer then: identifying the single transmission link as a faulty transmission link; resetting the timer; and outputting an identifier of the single transmission link.
摘要翻译： 隔离传输介质中的故障链路，包括包括通过具有多个传输链路的多链路传输介质接收原子数据单元的方法检测到错误状况，并且确定错误状况被隔离为单个 传输链路。 在由定时器指定的间隔内，确定单个传输链路是否已经被隔离为先前被隔离的传输链路指定的次数。 如果单个传输链路在由定时器指定的间隔内已经被隔离为失败的传输链路指定的次数，则：将单个传输链路识别为有故障的传输链路; 重置定时器; 并输出单个传输链路的标识符。
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