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公开(公告)号：US5732013A
公开(公告)日：1998-03-24
申请号：US780494
申请日：1997-01-08
CPC分类号： G11C8/10 , G11C17/126
摘要： A matrix memory with memory transistors arranged in rows and columns. The memory transistors can be addressed via word lines and bit lines. Control transistors are driven via control lines. The control transistors can short-circuit all of the columns of the cell array, i.e. the bit lines, except for the column in which a memory cell is located which is to be read out.
摘要翻译： 具有以行和列排列的存储晶体管的矩阵存储器。 可以通过字线和位线寻址存储晶体管。 控制晶体管通过控制线驱动。 控制晶体管可以短路单元阵列的所有列，即位线，除了要读出的存储单元所在的列之外。
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2.发明授权
公开(公告)号：US5825701A
公开(公告)日：1998-10-20
申请号：US682022
申请日：1996-07-16
IPC分类号： G11C11/412 , G11C7/12 , G11C17/12 , G11C7/00
CPC分类号： G11C7/12 , G11C17/126
摘要： The memory cell arrangement has MOS transistors (10) connected between bitlines (4, 4.sub.1) and connected row-by-row by means of selection lines (5). For pre-charging of all the bitlines (4, 4.sub.1) without a blocking of an access to these lines, further MOS transistors (20), connected between the bitlines (4, 4.sub.1) and a supply line (7), are provided, whose gate terminals (20.sub.2) are connected to a common pre-charging line (6).
摘要翻译： 存储单元布置具有连接在位线（4,41）之间并通过选择线（5）逐行连接的MOS晶体管（10）。 为了对所有位线（4,41）进行预充电而不阻塞访问这些线路，连接在位线（4,41）和电源线（7）之间的另外的MOS晶体管（20）被提供， 其栅极端子（202）连接到公共预充电线（6）。
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公开(公告)号：US5751742A
公开(公告)日：1998-05-12
申请号：US626512
申请日：1996-04-02
CPC分类号： G11C29/86 , G06F11/1008 , G11C29/88
摘要： In a serially working memory unit with a memory matrix, a row selection unit and a column selection unit are configured such that, given faulty rows or columns, only correctable, single errors or errors of few successive bits occur. This memory unit offers advantages particularly for read-only memories since, due to the memory contents that are already determined during manufacture, substitute rows or columns can thereby not be provided.
摘要翻译： 在具有存储器矩阵的串行工作存储器单元中，行选择单元和列选择单元被配置为使得给定有故障的行或列仅发生少数连续位的可校正的单个错误或错误。 该存储单元特别对于只读存储器提供了优点，因为由于在制造期间已经确定的存储器内容，因此可以不提供代替行或列。
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公开(公告)号：US06181183B2
公开(公告)日：2001-01-30
申请号：US09269047
申请日：1999-03-18
IPC分类号： H03K513
CPC分类号： H03K5/133
摘要： A circuit with a delay stage formed by an invertor having high-impedance transistors and, connected in series therewith, an invertor having low-impedance transistors MOS capacitors are provided between the gates of the transistors of the low-impedance invertor and the output of the delay stage. By means of this circuit, delay stages with steep edges can be realized with comparatively less outlay on components.
摘要翻译： 具有由具有高阻抗晶体管的反相器形成的延迟级的电路设置在低阻抗反相器的晶体管的栅极和 延迟阶段 通过该电路，可以实现具有陡峭边缘的延迟级，而在组件上的相对较少的支出。
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公开(公告)号：US6044006A
公开(公告)日：2000-03-28
申请号：US273648
申请日：1999-03-23
CPC分类号： G11C16/10
摘要： Memory cells are organized in cell fields in word lines and bit lines in the manner of a matrix. The bit lines are actuated by a bit decoder for loading with a mass potential, and by a blocking decoder for loading the bit lines with a blocking potential. The word lines are actuated by a word decoder for loading the word lines with a programming voltage or a protective voltage. The information value to be programmed is prestored in the cell field.
摘要翻译： 存储单元以矩阵的方式组织在字线和位线的单元格区域中。 位线由用于加载质量电位的位解码器以及用于加载具有阻塞电位的位线的阻塞解码器来驱动。 字线由字解码器驱动，用于用编程电压或保护电压加载字线。 要编程的信息值预先存储在单元格区域中。
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公开(公告)号：US07054469B2
公开(公告)日：2006-05-30
申请号：US10060431
申请日：2002-01-30
IPC分类号： G06K9/00
CPC分类号： G06K9/00053 , G01D5/24
摘要： A conductor layer is patterned into flat portions, for example of a fingerprint sensor that effects capacitive measurement. The conductor layer is fragmented in a lattice-like manner by cutouts so that an applied passivation layer rests on a base layer that is present beneath the conductor layer. The interlaminar shear strength of the passivation is increased in this way.
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公开(公告)号：US06365888B2
公开(公告)日：2002-04-02
申请号：US09782733
申请日：2001-02-13
IPC分类号： H01L2700
CPC分类号： G06K9/0002
摘要： A grid-shaped array of conductor areas is used for capacitive image acquisition. Shielding conductors are disposed in each case between the conductors that are provided for measurement. During a plurality of charging and discharging cycles, the potential is always carried along on the conductors belonging to a respective pixel in order to prevent displacement currents between the shielding capacitors. By way of example, a compensation line with a feedback operational amplifier can be used for identically altering the electrical potentials on the conductors.
摘要翻译： 导体区域的格子阵列用于电容图像采集。 每个壳体中的屏蔽导体都设置在用于测量的导体之间。 在多个充电和放电循环期间，为了防止屏蔽电容器之间的位移电流，电势总是沿着属于相应像素的导体承载。 作为示例，具有反馈运算放大器的补偿线可以用于相同地改变导体上的电位。
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8.发明授权Semiconductor component having double passivating layers formed of two passivating layers of different dielectric materials 失效半导体元件具有由两种不同介电材料的钝化层形成的双钝化层公开(公告)号：US06664612B2
公开(公告)日：2003-12-16
申请号：US09757328
申请日：2001-01-09
IPC分类号： H01L2358
CPC分类号： G06K9/0002 , H01L21/3145
摘要： A semiconductor component with passivation includes at least two double passivating layers, of which an uppermost is applied to a planar surface of a layer located therebelow. The double passivating layers include two layers of different dielectric materials, for example silicon oxide and silicon nitride. The respective thicknesses of the individual passivating layers can be adapted to dimensions of the structuring of the layer to which the passivation is applied. This produces a reliable passivation which is particularly suitable for capacitively measuring fingerprint sensors.
摘要翻译： 具有钝化的半导体部件包括至少两个双钝化层，其中最上层被施加到位于其下方的层的平坦表面。 双钝化层包括两层不同的介电材料，例如氧化硅和氮化硅。 单个钝化层的各自的厚度可以适应于施加钝化层的层的结构尺寸。 这产生了可靠的钝化，其特别适用于电容测量指纹传感器。
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9.发明授权公开(公告)号：US06714392B2
公开(公告)日：2004-03-30
申请号：US09906475
申请日：2001-07-16
申请人： Heinz Opolka , Paul-Werner Von Basse , Thomas Scheiter , Rainer Grossmann , Christian Peters , Reinhard Fischbach , Andreas Gaymann , Thomas Rosteck , Domagoj Siprak , Thorsten Sasse , Reinhard Göllner , Justin Bierner , Michael Melzl , Klaus Hammer , Markus Witte
发明人： Heinz Opolka , Paul-Werner Von Basse , Thomas Scheiter , Rainer Grossmann , Christian Peters , Reinhard Fischbach , Andreas Gaymann , Thomas Rosteck , Domagoj Siprak , Thorsten Sasse , Reinhard Göllner , Justin Bierner , Michael Melzl , Klaus Hammer , Markus Witte
IPC分类号： H05F300
CPC分类号： H01L23/60 , G06K9/00053 , H01L2924/0002 , H01L2924/00
摘要： An electronic component is described and has a dielectric layer which is constructed on a substrate, conductive surfaces that are constructed on the dielectric layer, and an electrically conductive guard structure. The guard structure is disposed in a plane above the conductive surfaces such that the conductive surfaces are not completely covered by the guard structure.
摘要翻译： 描述了电子部件，并且具有构造在基板上的介电层，构造在电介质层上的导电表面和导电保护结构。 防护结构设置在导电表面上方的平面中，使得导电表面不被保护结构完全覆盖。
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公开(公告)号：US4965464A
公开(公告)日：1990-10-23
申请号：US409577
申请日：1989-09-19
IPC分类号： H03K5/02 , H03K5/08 , H03K17/04 , H03K19/003 , H03K19/017 , H03K19/0185 , H03K19/0952
CPC分类号： H03K19/01721 , H03K19/00384 , H03K19/018535 , H03K19/0952 , H03K5/088
摘要： Power amplifier circuit for integrated digital circuits that combines the low permanent current consumption of a NOF push-pull output stage with the well-defined high level of a NON-NOFF amplifier stage having external clamp diode. An optimization of the leading edge is additionally achieved by fast drive and transient overdrive. A preceding inverter reduces the input capacitance of the overall circuit.
摘要翻译： 用于集成数字电路的功率放大器电路，其结合了NOF推挽输出级的低永久电流消耗与具有外部钳位二极管的NON-NOFF放大器级的明确定义的高电平。 通过快速驱动和瞬态过驱动还可以实现前沿优化。 前一个反相器降低了整个电路的输入电容。
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