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    DATA TRANSMISSION USING DELAYED TIMING SIGNALS
    1.
    发明申请
    DATA TRANSMISSION USING DELAYED TIMING SIGNALS 有权

    公开(公告)号：US20240372542A1

    公开(公告)日：2024-11-07

    申请号：US18638218

    申请日：2024-04-17

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely Tsern ,  Brian Leibowitz ,  Jared Zerbe

    IPC: H03K5/13 ,  G06F13/00 ,  G06F13/16 ,  G06F13/42 ,  G11C7/04 ,  G11C7/10 ,  G11C7/22 ,  G11C29/02

    Abstract: An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

    Data transmission using delayed timing signals
    2.
    发明授权
    Data transmission using delayed timing signals 有权

    公开(公告)号：US11451218B2

    公开(公告)日：2022-09-20

    申请号：US16880694

    申请日：2020-05-21

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely Tsern ,  Brian Leibowitz ,  Jared Zerbe

    IPC: H03K5/13 ,  G06F13/16 ,  G11C29/02 ,  G11C7/10 ,  G11C7/22 ,  G06F13/42 ,  G06F13/00 ,  G11C7/04

    Abstract: An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

    Methods and circuits for reducing clock jitter
    4.
    发明授权
    Methods and circuits for reducing clock jitter 有权
    减少时钟抖动的方法和电路

    公开(公告)号：US09397823B2

    公开(公告)日：2016-07-19

    申请号：US14518061

    申请日：2014-10-20

    Applicant: Rambus Inc.

    Inventor： Jared Zerbe ,  Teva Stone ,  Jihong Ren

    IPC: H04L7/02 ,  H03K5/1252 ,  H03L7/00

    CPC classification number: H04L7/02 ,  H03K5/1252 ,  H03L7/00

    Abstract: A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.

    Abstract translation: 通信系统包括时钟转发路径中的连续时间线性均衡器。 可以调整均衡器以使时钟抖动最小化，包括在使能时钟信号之后与前几个时钟沿相关联的抖动。 降低早期的抖动可以降低功耗和电路复杂度，否则需要快速打开系统。

    Data Transmission Using Delayed Timing Signals
    7.
    发明申请
    Data Transmission Using Delayed Timing Signals 审中-公开

    公开(公告)号：US20180145670A1

    公开(公告)日：2018-05-24

    申请号：US15824892

    申请日：2017-11-28

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely Tsern ,  Brian S. Leibowitz ,  Jared Zerbe

    IPC: H03K5/13 ,  G11C29/02 ,  G11C7/22 ,  G11C7/10 ,  G06F13/16 ,  G11C7/04 ,  G06F13/42 ,  G06F13/00

    Abstract: An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

    Methods and systems for transmitting data by modulating transmitter filter coefficients
    8.
    发明授权
    Methods and systems for transmitting data by modulating transmitter filter coefficients 有权
    通过调制发射机滤波器系数传输数据的方法和系统

    公开(公告)号：US09491011B2

    公开(公告)日：2016-11-08

    申请号：US14448006

    申请日：2014-07-31

    Applicant: Rambus Inc.

    Inventor： Jaeha Kim ,  Haechang Lee ,  Jung-Hoon Chun ,  Jared Zerbe

    IPC: H04B1/10 ,  H04L25/03 ,  H04L5/04 ,  H04B1/12

    CPC classification number: H04L25/03343 ,  H04B1/126 ,  H04L5/04 ,  H04L2025/03356 ,  H04L2025/03477 ,  H04L2025/03802

    Abstract: A signaling system supports main and auxiliary communication channels between integrated circuits in the same direction over a single link. An equalizing transmitter applies appropriate filter coefficients to minimize the impact of intersymbol interference when transmitting the main data over a communication channel. The transmitter modulates at least one of the filter coefficients with the auxiliary data to induce apparent ISI in the transmitted signal. A main receiver ignores the apparent ISI to recover the main data, while an auxiliary receiver detects and demodulates the apparent ISI to recover the auxiliary data. The auxiliary data may be encoded using spread-spectrum techniques to reduce the impact of the auxiliary data on the main data.

    Abstract translation: 信号系统通过单个链路在相同方向上支持集成电路之间的主要和辅助通信信道。 均衡发射机在通过通信信道发送主数据时，应用适当的滤波器系数来最小化符号间干扰的影响。 发射机利用辅助数据调制至少一个滤波器系数，以在发射信号中引起明显的ISI。 主接收机忽略明显的ISI以恢复主数据，而辅助接收机检测并解调明显的ISI以恢复辅助数据。 可以使用扩频技术对辅助数据进行编码，以减少辅助数据对主数据的影响。

    Methods and Systems for Transmitting Data by Modulating Transmitter Filter Coefficients
    9.
    发明申请
    Methods and Systems for Transmitting Data by Modulating Transmitter Filter Coefficients 有权
    通过调制发射机滤波器系数传输数据的方法和系统

    公开(公告)号：US20150207651A1

    公开(公告)日：2015-07-23

    申请号：US14448006

    申请日：2014-07-31

    Applicant: Rambus Inc.

    Inventor： Jaeha Kim ,  Haechang Lee ,  Jung-Hoon Chun ,  Jared Zerbe

    IPC: H04L25/03 ,  H04B1/12

    CPC classification number: H04L25/03343 ,  H04B1/126 ,  H04L5/04 ,  H04L2025/03356 ,  H04L2025/03477 ,  H04L2025/03802

    Abstract: A signaling system supports main and auxiliary communication channels between integrated circuits in the same direction over a single link. An equalizing transmitter applies appropriate filter coefficients to minimize the impact of intersymbol interference when transmitting the main data over a communication channel. The transmitter modulates at least one of the filter coefficients with the auxiliary data to induce apparent ISI in the transmitted signal. A main receiver ignores the apparent ISI to recover the main data, while an auxiliary receiver detects and demodulates the apparent ISI to recover the auxiliary data. The auxiliary data may be encoded using spread-spectrum techniques to reduce the impact of the auxiliary data on the main data.

    Abstract translation: 信号系统通过单个链路在相同方向上支持集成电路之间的主要和辅助通信信道。 均衡发射机在通过通信信道发送主数据时，应用适当的滤波器系数来最小化符号间干扰的影响。 发射机利用辅助数据调制至少一个滤波器系数，以在发射信号中引起明显的ISI。 主接收机忽略明显的ISI以恢复主数据，而辅助接收机检测并解调明显的ISI以恢复辅助数据。 可以使用扩频技术对辅助数据进行编码，以减少辅助数据对主数据的影响。

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