公开(公告)号：US20170019093A1

公开(公告)日：2017-01-19

申请号：US15157040

申请日：2016-05-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ryo KANDA ,  Koichi Yamazaki ,  Hiroshi Kuroiwa ,  Masatoshi Maeda ,  Tetsu Toda

IPC: H03K17/082 ,  H03K17/567 ,  H03K5/24 ,  H03K3/356 ,  H03K5/01

CPC classification number: H03K17/0822 ,  H01L23/528 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0922 ,  H01L29/0619 ,  H01L29/0642 ,  H01L29/0692 ,  H01L29/404 ,  H01L29/7823 ,  H01L29/7835 ,  H01L2224/0603 ,  H01L2224/48139 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2924/00014 ,  H03K3/356 ,  H03K3/356113 ,  H03K5/01 ,  H03K5/04 ,  H03K5/24 ,  H03K5/2472 ,  H03K5/2481 ,  H03K17/567 ,  H03K2217/0081 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A driver IC includes a ring-shaped termination area, and a first area and a second area that are respectively arranged outside and inside the termination area on a layout. A sense MOS that is arranged between a floating terminal and a first sense node and is driven at a power supply voltage is formed in the termination area. A fault detection circuit that detects presence of a fault when a voltage of the first sense node is higher than a decision voltage that has been determined in advance in a period of time that a low side driver is driving a low side transistor into an ON state is formed in the first area.

Abstract translation: 驱动器IC包括环形终止区域，以及分别布置在布局上的终止区域的内部和内部的第一区域和第二区域。 布置在浮动端子和第一感测节点之间并以电源电压驱动的感测MOS形成在终端区域中。 一种故障检测电路，当第一感测节点的电压高于在低侧驱动器将低侧晶体管驱动为导通状态的时间段中预先确定的判定电压时，检测故障的存在 形成在第一区域。

公开(公告)号：US10224921B2

公开(公告)日：2019-03-05

申请号：US15444876

申请日：2017-02-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ryo Kanda ,  Koichi Yamazaki ,  Hiroshi Kuroiwa ,  Masatoshi Maeda ,  Tetsu Toda

IPC: H03K17/082 ,  H03K17/567 ,  H03K5/01 ,  H03K5/24 ,  H03K3/356 ,  H03K5/04 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L23/528 ,  H01L23/00

Abstract: A driver IC includes a ring-shaped termination area, and a first area and a second area that are respectively arranged outside and inside the termination area on a layout. A sense MOS that is arranged between a floating terminal and a first sense node and is driven at a power supply voltage is formed in the termination area. A fault detection circuit that detects presence of a fault when a voltage of the first sense node is higher than a decision voltage that has been determined in advance in a period of time that a low side driver is driving a low side transistor into an ON state is formed in the first area.

公开(公告)号：US09837395B2

公开(公告)日：2017-12-05

申请号：US15097128

申请日：2016-04-12

Applicant: Renesas Electronics Corporation

Inventor： Hisashi Toyoda ,  Koichi Yamazaki ,  Koichi Arai ,  Tatsuhiro Seki

IPC: H01L29/15 ,  H01L31/0312 ,  H01L25/18 ,  H03K17/10 ,  H03K17/687 ,  H03K17/74 ,  H01L23/00 ,  H01L25/07 ,  H01L29/10 ,  H02P27/06

CPC classification number: H01L25/18 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L29/1095 ,  H01L2224/0603 ,  H01L2224/48137 ,  H01L2224/48225 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1203 ,  H01L2924/1207 ,  H01L2924/13062 ,  H01L2924/13091 ,  H02P27/06 ,  H03K17/102 ,  H03K17/6871 ,  H03K17/74 ,  H03K2017/6875 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor device includes a normally-on junction FET having a gate electrode, a source electrode and a drain electrode and a normally-off MOSFET having a gate electrode, a source electrode and a drain electrode. The source electrode of the junction FET is electrically connected to the drain electrode of the MOSFET, and the junction FET is thus connected to the MOSFET in series. The gate electrode of the junction FET is electrically connected to the gate electrode of the MOSFET.

公开(公告)号：US10854588B2

公开(公告)日：2020-12-01

申请号：US15824422

申请日：2017-11-28

Applicant: Renesas Electronics Corporation

Inventor： Hisashi Toyoda ,  Koichi Yamazaki ,  Koichi Arai ,  Tatsuhiro Seki

IPC: H01L25/18 ,  H03K17/10 ,  H03K17/687 ,  H03K17/74 ,  H01L23/00 ,  H01L25/07 ,  H01L29/10 ,  H02P27/06

Abstract: A semiconductor device includes a normally-on junction FET having a first gate electrode, a first source electrode and a first drain electrode, a normally-off MOSFET having a second gate electrode, a second source electrode and a second drain electrode, and a voltage applying unit which applies a voltage to the first gate electrode. The first source electrode of the junction FET is electrically connected to the second drain electrode of the MOSFET, and the junction FET is thus connected to the MOSFET in series, and the voltage applying unit applies a second voltage with a polarity opposite to that of a first voltage applied to the first gate electrode when the junction FET is brought into an off-state, to the first gate electrode when the MOSFET is in an on-state.

公开(公告)号：US10069439B2

公开(公告)日：2018-09-04

申请号：US15376374

申请日：2016-12-12

Applicant: Renesas Electronics Corporation

Inventor： Yoshihiko Yokoi ,  Yusuke Ojima ,  Koichi Yamazaki

IPC: H02M7/00 ,  H02M7/5387 ,  H03K17/082 ,  H02M7/538 ,  H02M7/53

Abstract: A power conversion system has a first coupling circuit including a wire between a controller and a high-side circuit and a second coupling circuit including a wire between the controller and a low-side circuit. The first coupling circuit has a diode having an anode coupled to a wire from the controller and a cathode coupled to a wire from the high-side circuit.

公开(公告)号：US09621151B2

公开(公告)日：2017-04-11

申请号：US15157040

申请日：2016-05-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ryo Kanda ,  Koichi Yamazaki ,  Hiroshi Kuroiwa ,  Masatoshi Maeda ,  Tetsu Toda

IPC: H03K3/00 ,  H03K17/082 ,  H03K3/356 ,  H03K5/01 ,  H03K5/24 ,  H03K17/567 ,  H01L23/528 ,  H01L23/00

CPC classification number: H03K17/0822 ,  H01L23/528 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0922 ,  H01L29/0619 ,  H01L29/0642 ,  H01L29/0692 ,  H01L29/404 ,  H01L29/7823 ,  H01L29/7835 ,  H01L2224/0603 ,  H01L2224/48139 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2924/00014 ,  H03K3/356 ,  H03K3/356113 ,  H03K5/01 ,  H03K5/04 ,  H03K5/24 ,  H03K5/2472 ,  H03K5/2481 ,  H03K17/567 ,  H03K2217/0081 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A driver IC includes a ring-shaped termination area, and a first area and a second area that are respectively arranged outside and inside the termination area on a layout. A sense MOS that is arranged between floating terminal and a first sense node and is driven at a power supply voltage is formed in the termination area. A fault detection circuit that detects presence of a fault when a voltage of the first sense node is higher than a decision voltage that has been deteLutined in advance in a period of time that a low side driver is driving a low side transistor into an ON state is formed in the first area.

公开(公告)号：US20160315075A1

公开(公告)日：2016-10-27

申请号：US15097128

申请日：2016-04-12

Applicant: Renesas Electronics Corporation

Inventor： Hisashi TOYODA ,  Koichi Yamazaki ,  Koichi Arai ,  Tatsuhiro Seki

IPC: H01L25/18 ,  H02P27/06 ,  H01L23/00 ,  H01L29/10 ,  H01L25/07

CPC classification number: H01L25/18 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L29/1095 ,  H01L2224/0603 ,  H01L2224/48137 ,  H01L2224/48225 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1203 ,  H01L2924/1207 ,  H01L2924/13062 ,  H01L2924/13091 ,  H02P27/06 ,  H03K17/102 ,  H03K17/6871 ,  H03K17/74 ,  H03K2017/6875 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor device includes a normally-on junction FET having a gate electrode, a source electrode and a drain electrode and a normally-off MOSFET having a gate electrode, a source electrode and a drain electrode. The source electrode of the junction FET is electrically connected to the drain electrode of the MOSFET, and the junction FET is thus connected to the MOSFET in series. The gate electrode of the junction FET is electrically connected to the gate electrode of the MOSFET.

Abstract translation: 半导体器件包括具有栅电极，源电极和漏电极的常栅结FET，以及具有栅电极，源电极和漏电极的常关MOSFET。 结FET的源电极电连接到MOSFET的漏电极，并且结FET被串联连接到MOSFET。 结FET的栅电极电连接到MOSFET的栅电极。