SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号:US20160148995A1

    公开(公告)日:2016-05-26

    申请号:US14977355

    申请日:2015-12-21

    Abstract: A semiconductor device including a first circuit region in which a first circuit whose power supply potential is a first voltage is formed; a second circuit region in which a second circuit whose power supply potential is a second voltage lower than the first voltage is formed a separation region which separates the first circuit region from the second circuit region; and a transistor which is located in the separation region and couples the second circuit to the first circuit and whose source and drain are of a first conductivity type, the separation region including an element separation film; a first field plate which overlaps with the element separation film in plan view; a plurality of conductive films which are provided over the first field plate.

    Abstract translation: 一种半导体器件,包括形成第一电路的第一电路区域,其中第一电路的电源电位为第一电压; 电源电位低于第一电压的第二电压的第二电路形成第二电路区域,该分离区域将第一电路区域与第二电路区域分离; 以及晶体管,其位于所述分离区域中并且将所述第二电路耦合到所述第一电路,并且其源极和漏极是第一导电类型,所述分离区域包括元件分离膜; 在平面图中与元件分离膜重叠的第一场板; 设置在第一场板上的多个导电膜。

    Semiconductor device and power control device

    公开(公告)号:US10396547B2

    公开(公告)日:2019-08-27

    申请号:US15702327

    申请日:2017-09-12

    Abstract: To realize a reduction in the number of parts in a system including a driver IC (semiconductor device). A high potential side power supply voltage is applied to a power supply application area. A high side area is formed with a circuit which includes a driver driving a high side transistor and is operated at a boot power supply voltage with a floating voltage as a reference. A low side area is formed with a circuit operated at a power supply voltage with a low potential side power supply voltage as a reference. A first termination area is disposed in a ring form so as to surround the power supply application area. A second termination area is disposed in a ring form so as to surround the high side area.

    Semiconductor device and manufacturing method thereof

    公开(公告)号:US10361189B2

    公开(公告)日:2019-07-23

    申请号:US15955819

    申请日:2018-04-18

    Inventor: Ryo Kanda

    Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate, a trench electrode provided in a trench, a trench insulating film provided between the trench electrode and the semiconductor substrate, a MOS electrode provided near the trench electrode, and a MOS insulating film provided between the MOS electrode and the semiconductor substrate, in which the semiconductor substrate includes a first semiconductor layer, a second semiconductor layer provided over the first semiconductor layer, a third semiconductor layer provided over the second semiconductor layer, a fourth semiconductor layer provided below the MOS electrode, and one and the other of fifth semiconductor layers provided on both sides of the fourth semiconductor layer, and in which the semiconductor device further includes a wiring layer that couples the one of the fifth semiconductor layers and the second semiconductor layer together.

    Semiconductor device with a trench electrode provided inside a trench formed on an upper surface of the semiconductor substrate and method of manufacturing the same

    公开(公告)号:US11227916B2

    公开(公告)日:2022-01-18

    申请号:US15934896

    申请日:2018-03-23

    Inventor: Ryo Kanda

    Abstract: According to an embodiment, a semiconductor device 1 includes a semiconductor substrate 50 including an upper surface, a trench electrode 22 provided inside a trench 20 formed on the upper surface, and a trench insulating film 21 provided between the trench electrode 22 and the semiconductor substrate 50. The semiconductor substrate 50 includes a first semiconductor layer of a first conductivity type, a lower end of the trench electrode 22 reaching the first semiconductor layer, a deep layer 19 of a second conductivity type partially provided on the first semiconductor layer in contact with the trench insulating film 21, a second semiconductor layer of the second conductivity type provided on the first semiconductor layer and on the deep layer 19 in contact with the trench insulating film 21, and a third semiconductor layer of the first conductivity type provided on the second semiconductor layer above the deep layer 19.

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