公开(公告)号：US20170373072A1

公开(公告)日：2017-12-28

申请号：US15682455

申请日：2017-08-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Nobuo TSUBOI

IPC: H01L27/11 ,  H01L29/49 ,  H01L23/535 ,  H01L29/786 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/1108 ,  H01L21/28008 ,  H01L21/28052 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823892 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/4916 ,  H01L29/4933 ,  H01L29/4941 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/786

Abstract: A semiconductor device can be reduced in size. The semiconductor device has a first conductivity type p type well layer extending in the X direction of the main surface of a semiconductor substrate; a reference potential wire coupled with the p type well layer, and extending in the X direction; first and second active regions arranged on the opposite sides of the reference potential wire in the Y direction; and a gate electrode layer extending in the Y direction in such a manner as to cross with the first and second active regions . Then, the gate electrode layer has a first gate electrode of a second conductivity type at the crossing part with the first active region, a second gate electrode of the second conductivity type at the crossing part with the second active region, and a non-doped electrode between the first gate electrode and the second gate electrode.

公开(公告)号：US20150206889A1

公开(公告)日：2015-07-23

申请号：US14672882

申请日：2015-03-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Nobuo TSUBOI

IPC: H01L27/11 ,  H01L23/482 ,  H01L23/50

CPC classification number: H01L27/1104 ,  H01L21/76808 ,  H01L23/4827 ,  H01L23/50 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1116 ,  H01L2924/0002 ,  Y10S257/903 ,  H01L2924/00

Abstract: A semiconductor device in which wirings are formed adequately and electrical couplings are made properly in an SRAM memory cell. In the SRAM memory cell of the semiconductor device, a via to be electrically coupled to a third wiring as a word line is directly coupled to a contact plug electrically coupled to the gate wiring part of an access transistor. Also, another via to be electrically coupled to the third wiring as the word line is directly coupled to a contact plug electrically coupled to the gate wiring part of another access transistor.

Abstract translation: 在SRAM存储单元中适当地形成布线的半导体器件和电耦合。 在半导体器件的SRAM存储单元中，要作为字线电耦合到第三布线的通孔直接耦合到电耦合到存取晶体管的栅极布线部分的接触插塞。 此外，当字线直接耦合到电耦合到另一个存取晶体管的栅极布线部分的接触插头时，另一通孔电耦合到第三布线。

公开(公告)号：US20180138204A1

公开(公告)日：2018-05-17

申请号：US15721901

申请日：2017-09-30

Applicant: Renesas Electronics Corporation

Inventor： Nobuo TSUBOI ,  Yoshiki YAMAMOTO

IPC: H01L27/12 ,  G05F1/625 ,  H01L29/78 ,  H03K17/687

CPC classification number: H01L27/1203 ,  G05F1/625 ,  H01L21/8238 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/02 ,  H01L27/0207 ,  H01L27/1244 ,  H01L29/41733 ,  H01L29/78 ,  H03K17/687

Abstract: Reliability of a semiconductor device is improved. A p-type MISFET of a thin film SOI type is formed in an SOI substrate including a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor layer on the insulating layer, and n+-type semiconductor regions which are source and drain region of the p-type MISFET are formed in the semiconductor layer and an epitaxial layer on the semiconductor layer. A semiconductor layer is formed via the insulating layer below the p-type MISFET formed in the n-type well region of the semiconductor substrate. In an n-type tap region which is a power supply region of the n-type well region, a silicide layer is formed on a main surface of the n-type well region without interposing the epitaxial layer therebetween.

公开(公告)号：US20170345750A1

公开(公告)日：2017-11-30

申请号：US15583829

申请日：2017-05-01

Applicant: Renesas Electronics Corporation

Inventor： Nobuo TSUBOI

IPC: H01L23/528 ,  H01L21/762 ,  H01L21/84 ,  H01L23/522 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L27/1207 ,  G11C11/412 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/84 ,  H01L23/528 ,  H01L27/088 ,  H01L27/105 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/66772

Abstract: Characteristics of a semiconductor device are improved. The semiconductor device is configured to include an SOI substrate including an active region and an element isolation region (element isolation insulating film), a gate electrode formed in the active region via a gate insulating film, and a dummy gate electrode formed in the element isolation region. A dummy sidewall film is formed on both sides of the dummy gate electrode, and is arranged to match or overlap a boundary between the active region and the element isolation region (element isolation insulating film). According to such a configuration, a plug can be prevented from deeply reaching, for example, an insulating layer and a support substrate even when a contact hole is formed to be shifted.

公开(公告)号：US20190393248A1

公开(公告)日：2019-12-26

申请号：US16564744

申请日：2019-09-09

Applicant: Renesas Electronics Corporation

Inventor： Nobuo TSUBOI

IPC: H01L27/12 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/84

Abstract: A semiconductor device includes an SOI substrate having an active region and an element isolation region adjacent to the active region, and including a support substrate, an insulating layer formed on the support substrate, and a semiconductor layer formed on the insulating layer, a trench formed in the element isolation region, and penetrating the semiconductor layer and the insulating layer so as to reach the support substrate, an element isolation insulating film embedded in the trench, the element isolation insulating film being made of silicon oxide film, a gate electrode formed on the semiconductor layer in the active region via a gate insulating film, a sidewall film formed on both sides of the gate electrode in cross-section view, the sidewall film being comprised of a first film made of silicon oxide film, and a second film made of silicon nitride film.

公开(公告)号：US20190181157A1

公开(公告)日：2019-06-13

申请号：US16154432

申请日：2018-10-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Nobuo TSUBOI

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/51 ,  H01L27/092 ,  H01L29/78 ,  H01L21/768 ,  H01L21/762 ,  H01L21/033 ,  H01L21/8238

Abstract: There is provided with the following semiconductor device to improve its reliability. In a SOI substrate including a semiconductor substrate, an insulating layer, and a semiconductor layer, a diffusion region is formed in the semiconductor layer and a plug electrically connected to the diffusion region is formed on the diffusion region. An element isolation portion is formed within the semiconductor substrate and a trench is formed in the element isolation portion. The lowest part of the bottom of the trench is lower than the surface of the semiconductor substrate and a sidewall spacer is formed in the side portion of the trench to cover the side surface of the insulating layer. As the result, even when the plug is formed in a deviated position, a disadvantage of conducting the semiconductor layer with the semiconductor substrate can be suppressed.

公开(公告)号：US20170012048A1

公开(公告)日：2017-01-12

申请号：US15157078

申请日：2016-05-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Nobuo TSUBOI

IPC: H01L27/11 ,  H01L29/786 ,  H01L21/28 ,  H01L29/49 ,  H01L23/535

CPC classification number: H01L27/1108 ,  H01L21/28008 ,  H01L21/28052 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823892 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/4916 ,  H01L29/4933 ,  H01L29/4941 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/786

Abstract: A semiconductor device can be reduced in size. The semiconductor device has a first conductivity type p type well layer extending in the X direction of the main surface of a semiconductor substrate; a reference potential wire coupled with the p type well layer, and extending in the X direction; first and second active regions arranged on the opposite sides of the reference potential wire in the Y direction; and a gate electrode layer extending in the Y direction in such a manner as to cross with the first and second active regions. Then, the gate electrode layer has a first gate electrode of a second conductivity type at the crossing part with the first active region, a second gate electrode of the second conductivity type at the crossing part with the second active region, and a non-doped electrode between the first gate electrode and the second gate electrode.

Abstract translation: 可以减小半导体器件的尺寸。 半导体器件具有在半导体衬底的主表面的X方向上延伸的第一导电型p型阱层; 与p型阱层耦合并沿X方向延伸的参考电位线; 布置在参考电位线的相反侧的Y方向上的第一和第二有源区; 以及栅极电极层，其以与第一和第二有源区域交叉的方式在Y方向延伸。 然后，栅电极层具有与第一有源区交叉的第二导电类型的第一栅电极，与第二有源区交叉的第二导电类型的第二栅电极和非掺杂 电极在第一栅极电极和第二栅极电极之间。

公开(公告)号：US20160188787A1

公开(公告)日：2016-06-30

申请号：US15064387

申请日：2016-03-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroyuki MOMONO ,  Nobuo TSUBOI

IPC: G06F17/50 ,  H01L27/146

CPC classification number: G06F17/5081 ,  G06F17/5072 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14645

Abstract: A solid-state imaging device includes pixels respectively having photoelectric conversion units and arranged in matrix in basic pattern units, and an optical member arranged on the incidence side of incident light than the pixels and having constituent elements respectively corresponding to the pixels. The pixels include first, second and third wavelength range light pixels. Each basic pattern is comprised of a combined arrangement pattern of the wavelength range light pixels. Misregistration constituent elements with the occurrence of misregistration exist in the constituent elements. The misregistration increases toward the misregistration constituent elements separated from a center position of a pixel array of the pixels. The misregistration of the misregistration constituent element for the first wavelength range light pixel and that of the misregistration constituent element for the third wavelength range light pixel are smaller and larger than that of the misregistration constituent element for the second wavelength range light pixel, respectively.

公开(公告)号：US20150123229A1

公开(公告)日：2015-05-07

申请号：US14529061

申请日：2014-10-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroyuki MOMONO ,  Nobuo TSUBOI

IPC: H01L27/146 ,  G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5072 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14645

Abstract: A solid-state imaging device includes pixels respectively having photoelectric conversion units and arranged in matrix in basic pattern units, and an optical member arranged on the incidence side of incident light than the pixels and having constituent elements respectively corresponding to the pixels. The pixels include first, second and third wavelength range light pixels. Each basic pattern is comprised of a combined arrangement pattern of the wavelength range light pixels. Misregistration constituent elements with the occurrence of misregistration exist in the constituent elements. The misregistration increases toward the misregistration constituent elements separated from a center position of a pixel array of the pixels. The misregistration of the misregistration constituent element for the first wavelength range light pixel and that of the misregistration constituent element for the third wavelength range light pixel are smaller and larger than that of the misregistration constituent element for the second wavelength range light pixel, respectively.

Abstract translation: 固态成像装置包括分别具有光电转换单元并以基本图案单位矩阵排列的像素，以及配置在入射光的入射侧的光学部件，并且具有分别对应于像素的构成元件。 像素包括第一，第二和第三波长范围的光像素。 每个基本图案由波长范围的光像素的组合布置图案组成。 在组成要素中存在配对错误发生的注册组成要素。 不对准性增加到与像素的像素阵列的中心位置分离的对准构件。 针对第一波长范围的光像素和第三波长范围的光像素的不对准构成元件的重合配置元件的对准分别比分别用于第二波长范围的光像素的不对准构成元件的对准分配要小。