公开(公告)号：US09558826B2

公开(公告)日：2017-01-31

申请号：US15152391

申请日：2016-05-11

Applicant: Renesas Electronics Corporation

Inventor： Tsuyoshi Arigane ,  Daisuke Okada ,  Digh Hisamoto

IPC: G11C16/04 ,  G11C16/14 ,  H01L29/423 ,  H01L27/115 ,  H01L29/51 ,  G11C16/34

Abstract: A first potential and a second potential lower than the first potential are applied to a first end of a memory gate electrode part of the nonvolatile memory and to a second end of the memory gate electrode part, respectively, so that a current is caused to flow in a direction in which the memory gate electrode part extends, then, a hole is injected from the memory gate electrode part into a charge accumulating part below it, therefore, an electron accumulated in the charge accumulating part is eliminated. By causing the current to flow through the memory gate electrode part of a memory cell region as described above, Joule heat can be generated to heat the memory cell. Consequently, in the erasing by a FN tunneling method in which the erasing characteristics degrade at a low temperature, the erasing speed can be improved by heating the memory gate electrode part.

公开(公告)号：US09508837B2

公开(公告)日：2016-11-29

申请号：US15004972

申请日：2016-01-24

Applicant: Renesas Electronics Corporation

Inventor： Tsuyoshi Arigane ,  Daisuke Okada ,  Digh Hisamoto

IPC: H01L21/3205 ,  H01L29/66 ,  H01L27/115 ,  H01L29/51 ,  H01L29/423 ,  H01L21/28 ,  H01L29/792

CPC classification number: H01L29/66833 ,  H01L21/2815 ,  H01L21/28158 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/792

Abstract: To provide a semiconductor device having a nonvolatile memory improved in characteristics. In the semiconductor device, a nonvolatile memory has a high-k insulating film (high dielectric constant film) between a control gate electrode portion and a memory gate electrode portion and a transistor of a peripheral circuit region has a high-k/metal configuration. The high-k insulating film arranged between the control gate electrode portion and the memory gate electrode portion relaxes an electric field intensity at the end portion (corner portion) of the memory gate electrode portion on the side of the control gate electrode portion. This results in reduction in uneven distribution of charges in a charge accumulation portion (silicon nitride film) and improvement in erase accuracy.

公开(公告)号：US09117849B2

公开(公告)日：2015-08-25

申请号：US14325472

申请日：2014-07-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kenichi Akita ,  Daisuke Okada ,  Keisuke Kuwahara ,  Yasufumi Morimoto ,  Yasuhiro Shimamoto ,  Kan Yasui ,  Tsuyoshi Arigane ,  Tetsuya Ishimaru

IPC: H01L21/8238 ,  H01L29/66 ,  H01L27/115 ,  H01L29/792

CPC classification number: H01L29/66833 ,  H01L27/115 ,  H01L27/11563 ,  H01L27/11568 ,  H01L29/792

Abstract: A method and apparatus of forming a nonvolatile semiconductor device including forming a first gate insulating film on a main surface of a first semiconductor region, forming a first gate electrode on the first gate insulating film, forming a second gate insulating film, forming a second gate electrode over a first side surface of the first gate electrode, selectively removing the second gate insulating film, etching the second gate insulating film kept between the second gate electrode and a main surface of the first semiconductor region in order to form an etched charge storage layer, introducing first impurities in the first semiconductor region in a self-aligned manner to the second gate electrode in order to form a second semiconductor region, annealing the semiconductor substrate to extend the second semiconductor region to an area under the second gate electrode.

Abstract translation: 一种形成非易失性半导体器件的方法和装置，包括在第一半导体区域的主表面上形成第一栅极绝缘膜，在第一栅极绝缘膜上形成第一栅电极，形成第二栅极绝缘膜，形成第二栅极 电极，在第一栅电极的第一侧表面上，选择性地去除第二栅极绝缘膜，蚀刻保持在第二栅极电极和第一半导体区域的主表面之间的第二栅极绝缘膜，以形成蚀刻电荷存储层 为了形成第二半导体区域，以自对准的方式将第一半导体区域中的第一杂质引入第二栅电极，使半导体衬底退火，将第二半导体区域延伸到第二栅电极下方的区域。

公开(公告)号：US20140322874A1

公开(公告)日：2014-10-30

申请号：US14325472

申请日：2014-07-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kenichi Akita ,  Daisuke Okada ,  Keisuke Kuwahara ,  Yasufumi Morimoto ,  Yasuhiro Shimamoto ,  Kan Yasui ,  Tsuyoshi Arigane ,  Tetsuya Ishimaru

IPC: H01L29/66 ,  H01L27/115

CPC classification number: H01L29/66833 ,  H01L27/115 ,  H01L27/11563 ,  H01L27/11568 ,  H01L29/792

Abstract: A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.

Abstract translation: 插入在存储栅电极和半导体衬底之间的电荷存储层形成为比存储栅电极的栅极长度或绝缘膜的长度短，以使电荷存储层和源极区域的重叠量成为 小于40nm。 因此，在写入状态下，由于在电荷存储层中局部存在的电子和空穴的横向的移动减少，因此可以降低保持高温时的阈值电压的变化。 此外，有效沟道长度为30nm以下，以减少空穴的表观量，使得电子与电荷存储层中的空穴的耦合减小; 因此，可以降低在室温下保持时的阈值电压的变化。

公开(公告)号：US09589638B2

公开(公告)日：2017-03-07

申请号：US15152391

申请日：2016-05-11

Applicant: Renesas Electronics Corporation

Inventor： Tsuyoshi Arigane ,  Daisuke Okada ,  Digh Hisamoto

IPC: G11C16/04 ,  G11C16/14 ,  H01L29/423 ,  H01L27/115 ,  H01L29/51 ,  G11C16/34

CPC classification number: G11C16/0466 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/344 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/511 ,  H01L29/518 ,  H01L29/792

Abstract: A first potential and a second potential lower than the first potential are applied to a first end of a memory gate electrode part of the nonvolatile memory and to a second end of the memory gate electrode part, respectively, so that a current is caused to flow in a direction in which the memory gate electrode part extends, then, a hole is injected from the memory gate electrode part into a charge accumulating part below it, therefore, an electron accumulated in the charge accumulating part is eliminated. By causing the current to flow through the memory gate electrode part of a memory cell region as described above, Joule heat can be generated to heat the memory cell. Consequently, in the erasing by a FN tunneling method in which the erasing characteristics degrade at a low temperature, the erasing speed can be improved by heating the memory gate electrode part.

Abstract translation: 低于第一电位的第一电势和第二电位被分别施加到非易失性存储器的存储栅电极部分的第一端和存储栅电极部分的第二端，使得电流流过 在存储栅电极部分延伸的方向上，从存储栅电极部分注入空穴到其下方的电荷累积部分，因此，积累在电荷累积部分中的电子被消除。 通过使电流流过如上所述的存储单元区域的存储栅电极部分，可以产生焦耳热以加热存储单元。 因此，在擦除特性在低温下劣化的FN隧穿法的擦除中，通过加热存储栅电极部分可以提高擦除速度。

公开(公告)号：US09257446B2

公开(公告)日：2016-02-09

申请号：US14548595

申请日：2014-11-20

Applicant: Renesas Electronics Corporation

Inventor： Tsuyoshi Arigane ,  Daisuke Okada ,  Digh Hisamoto

IPC: H01L27/115 ,  H01L29/51 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L29/66833 ,  H01L21/2815 ,  H01L21/28158 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/792

Abstract: To provide a semiconductor device having a nonvolatile memory improved in characteristics. In the semiconductor device, a nonvolatile memory has a high-k insulating film (high dielectric constant film) between a control gate electrode portion and a memory gate electrode portion and a transistor of a peripheral circuit region has a high-k/metal configuration. The high-k insulating film arranged between the control gate electrode portion and the memory gate electrode portion relaxes an electric field intensity at the end portion (corner portion) of the memory gate electrode portion on the side of the control gate electrode portion. This results in reduction in uneven distribution of charges in a charge accumulation portion (silicon nitride film) and improvement in erase accuracy.

Abstract translation: 提供具有改善特性的非易失性存储器的半导体器件。 在半导体器件中，非易失性存储器在控制栅电极部分和存储栅电极部分之间具有高k绝缘膜（高介电常数膜），并且外围电路区域的晶体管具有高k /金属构造。 布置在控制栅电极部分和存储栅电极部分之间的高k绝缘膜松弛在控制栅电极部分一侧的存储栅电极部分的端部（拐角部分）的电场强度。 这导致电荷累积部分（氮化硅膜）中电荷的不均匀分布的减少和擦除精度的提高。

公开(公告)号：US09515082B2

公开(公告)日：2016-12-06

申请号：US14664493

申请日：2015-03-20

Applicant: Renesas Electronics Corporation

Inventor： Tsuyoshi Arigane ,  Digh Hisamoto ,  Daisuke Okada

IPC: H01L21/336 ,  H01L27/115 ,  H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28 ,  H01L21/762

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L21/76224 ,  H01L21/76229 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/792

Abstract: A memory gate is formed of a first memory gate including a second gate insulating film made of a second insulating film and a first memory gate electrode, and a second memory gate including a third gate insulating film made of a third insulating film and a second memory gate electrode. In addition, the lower surface of the second memory gate electrode is located lower in level than the lower surface of the first memory gate electrode. As a result, during an erase operation, an electric field is concentrated on the corner portion of the first memory gate electrode which is located closer to a selection gate and a semiconductor substrate and on the corner portion of the second memory gate electrode which is located closer to the first memory gate and the semiconductor substrate. This allows easy injection of holes into each of the second and third insulating films.

Abstract translation: 存储栅极由包括由第二绝缘膜和第一存储栅电极构成的第二栅绝缘膜的第一存储栅形成，以及包括由第三绝缘膜和第二存储器构成的第三栅绝缘膜的第二存储栅 栅电极。 此外，第二存储栅电极的下表面位于比第一存储栅电极的下表面更低的电平。 结果，在擦除操作期间，电场集中在位于更靠近选择栅极和半导体衬底的位于第一存储栅电极的角部上，并且位于位于第二存储栅电极的拐角部分 更靠近第一存储器栅极和半导体衬底。 这允许容易地将孔注入到每个第二和第三绝缘膜中。

公开(公告)号：US20160141396A1

公开(公告)日：2016-05-19

申请号：US15004972

申请日：2016-01-24

Applicant: Renesas Electronics Corporation

Inventor： Tsuyoshi Arigane ,  Daisuke Okada ,  Digh Hisamoto

IPC: H01L29/66 ,  H01L29/423

CPC classification number: H01L29/66833 ,  H01L21/2815 ,  H01L21/28158 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/792

Abstract: To provide a semiconductor device having a nonvolatile memory improved in characteristics. In the semiconductor device, a nonvolatile memory has a high-k insulating film (high dielectric constant film) between a control gate electrode portion and a memory gate electrode portion and a transistor of a peripheral circuit region has a high-k/metal configuration. The high-k insulating film arranged between the control gate electrode portion and the memory gate electrode portion relaxes an electric field intensity at the end portion (corner portion) of the memory gate electrode portion on the side of the control gate electrode portion. This results in reduction in uneven distribution of charges in a charge accumulation portion (silicon nitride film) and improvement in erase accuracy.

公开(公告)号：US20150145023A1

公开(公告)日：2015-05-28

申请号：US14548595

申请日：2014-11-20

Applicant: Renesas Electronics Corporation

Inventor： Tsuyoshi Arigane ,  Daisuke Okada ,  Digh Hisamoto

IPC: H01L27/115 ,  H01L29/423 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L29/66833 ,  H01L21/2815 ,  H01L21/28158 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/792

Abstract: To provide a semiconductor device having a nonvolatile memory improved in characteristics. In the semiconductor device, a nonvolatile memory has a high-k insulating film (high dielectric constant film) between a control gate electrode portion and a memory gate electrode portion and a transistor of a peripheral circuit region has a high-k/metal configuration. The high-k insulating film arranged between the control gate electrode portion and the memory gate electrode portion relaxes an electric field intensity at the end portion (corner portion) of the memory gate electrode portion on the side of the control gate electrode portion. This results in reduction in uneven distribution of charges in a charge accumulation portion (silicon nitride film) and improvement in erase accuracy.

Abstract translation: 提供具有改善特性的非易失性存储器的半导体器件。 在半导体器件中，非易失性存储器在控制栅电极部分和存储栅电极部分之间具有高k绝缘膜（高介电常数膜），并且外围电路区域的晶体管具有高k /金属构造。 布置在控制栅电极部分和存储栅电极部分之间的高k绝缘膜松弛在控制栅电极部分一侧的存储栅电极部分的端部（拐角部分）的电场强度。 这导致电荷累积部分（氮化硅膜）中电荷的不均匀分布的减少和擦除精度的提高。

公开(公告)号：US20140092688A1

公开(公告)日：2014-04-03

申请号：US14100302

申请日：2013-12-09

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya Ishimaru ,  Yasuhiro Shimamoto ,  Hideo Kasai ,  Yutaka Okuyama ,  Tsuyoshi Arigane

IPC: G11C16/10 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/0466 ,  G11C16/14 ,  G11C16/30 ,  H01L27/11563 ,  H01L29/42344

Abstract: In a split gate MONOS memory which carries out rewrite by hot carrier injection, retention characteristics are improved. A select gate electrode of a memory cell is connected to a select gate line, and a memory gate electrode is connected to a memory gate line. A drain region is connected to a bit line, and a source region is connected to a source line. Furthermore, a well line is connected to a p type well region in which the memory cell is formed. When write to the memory cell is to be carried out, write by a source side injection method is carried out while applying a negative voltage to the p type well region via the well line.

Abstract translation: 在通过热载流子注入进行重写的分闸门MONOS存储器中，保持特性得到改善。 存储单元的选择栅电极连接到选择栅极线，并且存储栅电极连接到存储栅极线。 漏极区域连接到位线，并且源极区域连接到源极线。 此外，阱线连接到其中形成存储单元的p型阱区域。 当要对存储单元进行写入时，通过源极侧注入方法进行写入，同时通过阱线向p型阱区域施加负电压。