公开(公告)号：US10170190B2

公开(公告)日：2019-01-01

申请号：US15676778

申请日：2017-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Wan Nam ,  Dae-Seok Byeon ,  Chi-Weon Yoon ,  Hae-Suk Shin

IPC: G11C16/06 ,  G06F3/06

Abstract: A method of controlling the operation of a memory controller includes, in a read operation of a non-volatile memory device, the memory controller counting a selected read count of a selected string in a selected memory block and/or counting a non-selected read count of a non-selected string in the selected memory block. The memory controller performs a reclaim operation of the selected memory block when the selected read count and/or the non-selected read count exceeds a read threshold. To move data of the selected memory block to another memory block by the reclaim operation, the memory controller may copy the data of the selected memory block to another block by using a changed page address.

公开(公告)号：US09761315B2

公开(公告)日：2017-09-12

申请号：US15357291

申请日：2016-11-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Wan Nam ,  Doo-Hyun Kim ,  Dae-Seok Byeon ,  Chi-Weon Yoon

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  G11C16/06 ,  G11C16/34 ,  G11C16/10 ,  H01L27/11582 ,  G11C16/12

Abstract: A memory device is provided as follows. A memory cell region includes a plurality of blocks, each block including a plurality of NAND strings. A control logic divides the plurality of blocks into a plurality of block regions based on a smaller distance of a first distance with respect to a first edge of the memory cell region and a second distance with respect to a second edge of the memory cell region and controls an operation performed on the memory cell region using a plurality of bias sets of operation parameters for the operation. Each bias set is associated with one of the block regions.

公开(公告)号：US09633726B2

公开(公告)日：2017-04-25

申请号：US14716558

申请日：2015-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Kook Park ,  Chi-Weon Yoon ,  Yeong-Taek Lee

IPC: G11C13/00 ,  G11C11/16 ,  G11C11/56

CPC classification number: G11C13/0069 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1677 ,  G11C11/1693 ,  G11C11/56 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0097 ,  G11C2013/0088

Abstract: A method of operating a resistive memory device having a plurality of word lines and a plurality of bit lines includes selecting one or more first memory cells connected to a first bit line, selecting one or more second memory cells connected to a second bit line, and simultaneously performing a reset write operation on the first and second memory cells using a first write driver.

公开(公告)号：US10892019B2

公开(公告)日：2021-01-12

申请号：US16788638

申请日：2020-02-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Wan Nam ,  Dong-Hun Kwak ,  Chi-Weon Yoon

IPC: G11C16/04 ,  G11C16/16 ,  G11C8/12 ,  H01L27/11573 ,  H01L27/11582 ,  G11C16/14

Abstract: A method of operating a nonvolatile memory device includes erasing data within a NAND string of memory cells within the memory device by applying a non-zero erase voltage to a source/drain terminal at a first end of the NAND string. This erase voltage is applied concurrently with establishing gate-induced drain leakage (GIDL) in a pair of selection transistors within the NAND string. This GIDL can occur by applying unequal and non-zero first and second voltages to respective first and second gate terminals of the pair of selection transistors. The selection transistors can be string selection transistors or ground selection transistors.

公开(公告)号：US09437290B2

公开(公告)日：2016-09-06

申请号：US14631182

申请日：2015-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-Kyu Lee ,  Dae-Seok Byeon ,  Hyo-Jin Kwon ,  Hyun-Kook Park ,  Chi-Weon Yoon ,  Yeong-Taek Lee

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56

CPC classification number: G11C13/0033 ,  G11C11/5607 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007

Abstract: A method of operating a resistive memory device including a plurality of memory cells comprises determining whether to perform a refresh operation on memory cells in a memory cell array; determining a resistance state of each of at least some of the memory cells; and performing a re-writing operation on a first memory cell having a resistance state from among a plurality of resistance states that is equal to or less than a critical resistance level.

Abstract translation: 一种操作包括多个存储单元的电阻式存储器件的方法包括：确定是否对存储单元阵列中的存储器单元执行刷新操作; 确定所述至少一些所述存储器单元中的每一个的电阻状态; 以及在等于或小于临界电阻水平的多个电阻状态之中对具有电阻状态的第一存储单元执行重写操作。

公开(公告)号：US11164637B2

公开(公告)日：2021-11-02

申请号：US17015525

申请日：2020-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Wan Nam ,  Dong-Hun Kwak ,  Chi-Weon Yoon

IPC: G11C16/04 ,  G11C16/16 ,  G11C8/12 ,  H01L27/11573 ,  H01L27/11582 ,  G11C16/14

Abstract: A nonvolatile memory device includes a memory cell region, a peripheral circuit region, a memory block in the memory cell region, and a control circuit in the peripheral circuit region. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes a plurality of memory cells disposed in a vertical direction. The control circuit applies an erase voltage to an erase source terminal of the memory block, and applies a first voltage to a first selection line among a plurality of selection lines in the memory block. The first voltage is higher than the erase voltage. The first selection line is disposed closest to the erase source terminal among the plurality of selection lines and is used for selecting the memory block as an erase target block.

公开(公告)号：US20200185038A1

公开(公告)日：2020-06-11

申请号：US16788638

申请日：2020-02-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Wan Nam ,  Dong-Hun Kwak ,  Chi-Weon Yoon

IPC: G11C16/16 ,  G11C16/04 ,  H01L27/11582 ,  H01L27/11573

Abstract: A method of operating a nonvolatile memory device includes erasing data within a NAND string of memory cells within the memory device by applying a non-zero erase voltage to a source/drain terminal at a first end of the NAND string. This erase voltage is applied concurrently with establishing gate-induced drain leakage (GIDL) in a pair of selection transistors within the NAND string. This GIDL can occur by applying unequal and non-zero first and second voltages to respective first and second gate terminals of the pair of selection transistors. The selection transistors can be string selection transistors or ground selection transistors.

公开(公告)号：US10600487B2

公开(公告)日：2020-03-24

申请号：US16205334

申请日：2018-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Wan Nam ,  Dong-Hun Kwak ,  Chi-Weon Yoon

IPC: G11C16/04 ,  G11C16/16 ,  G11C8/12 ,  H01L27/11573 ,  H01L27/11582 ,  G11C16/14

Abstract: A method of operating a nonvolatile memory device includes erasing data within a NAND string of memory cells within the memory device by applying a non-zero erase voltage to a source/drain terminal at a first end of the NAND string. This erase voltage is applied concurrently with establishing gate-induced drain leakage (GIDL) in a pair of selection transistors within the NAND string. This GIDL can occur by applying unequal and non-zero first and second voltages to respective first and second gate terminals of the pair of selection transistors. The selection transistors can be string selection transistors or ground selection transistors.

公开(公告)号：US09530494B2

公开(公告)日：2016-12-27

申请号：US14697244

申请日：2015-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-Kyu Lee ,  Dae-Seok Byeon ,  Yeong-Taek Lee ,  Chi-Weon Yoon ,  Hyun-Kook Park ,  Hyo-Jin Kwon

IPC: G11C16/10 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0033 ,  G11C13/0035 ,  G11C16/10 ,  G11C2013/0092

Abstract: A method of operating a memory device, which includes of memory cells respectively arranged in regions where first signal lines and second lines cross each other, includes determining a plurality of pulses so that each of the plurality of pulses that are sequentially applied to a selected memory cell among the plurality of memory cells is changed according to a number of times of executing programming loops. In response to the change of the plurality of pulses, at least one of a first inhibit voltage and a second inhibit voltage is determined so that a voltage level of at least one of the first and second inhibit voltages that are respectively applied to unselected first and second signal lines connected to unselected memory cells among the plurality of memory cells is changed according to the number of times of executing the programming loops.

Abstract translation: 一种操作存储器件的方法，所述存储器件包括分别布置在第一信号线和第二线彼此交叉的区域中的存储器单元，包括确定多个脉冲，使得多个脉冲中的每一个顺序地施加到选择的存储器 根据执行编程循环的次数来改变多个存储单元之间的单元。 响应于多个脉冲的变化，确定第一禁止电压和第二禁止电压中的至少一个，使得分别施加到未选择的第一和第二禁止电压中的至少一个的电压电平， 连接到多个存储单元之间的未选择的存储单元的第二信号线根据执行编程循环的次数而改变。

公开(公告)号：US09508441B1

公开(公告)日：2016-11-29

申请号：US15131237

申请日：2016-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Wan Nam ,  Dae-Seok Byeon ,  Chi-Weon Yoon

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/08

CPC classification number: G11C16/10 ,  G11C16/0483

Abstract: A memory device includes a memory cell array including a plurality of NAND strings, wherein each of the NAND strings includes a ground selection transistor connected to a ground selection line, memory cells connected to word lines, and a string selection transistor connected to a string selection line, wherein the ground selection line, the word lines, and the string selection line are vertically stacked on a substrate. A control logic adjusts a ground selection line voltage applied to the ground selection line or a string selection line voltage applied to the string selection line to a negative level in at least a portion of a program section during which a program operation related to a memory cell selected from among the memory cells is performed.

Abstract translation: 存储器件包括包括多个NAND串的存储单元阵列，其中每个NAND串包括连接到接地选择线的接地选择晶体管，连接到字线的存储单元和连接到串选择的串选择晶体管 线，其中地面选择线，字线和弦选择线垂直地堆叠在基底上。 控制逻辑在施加到接地选择线的接地选择线电压或施加到串选择线的串选择线电压在程序部分的至少一部分中将与存储器单元相关的程序操作 从存储单元中进行选择。