公开(公告)号：US10535401B2

公开(公告)日：2020-01-14

申请号：US16000413

申请日：2018-06-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lei Lin ,  Zhuojie Li ,  Henry Chin ,  Cynthia Hsu

IPC: G11C16/06 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C29/12 ,  G11C16/08

Abstract: An apparatus is provided that includes a plurality of memory cells, a programming circuit configured to apply a plurality of programming pulses to the memory cells, and a scanning circuit configured to repeatedly switch between performing an n-state bitscan after each programming pulse until first predetermined criteria are satisfied, and performing an m-state bitscan after each programming pulse until second predetermined criteria are satisfied, where m>n, and n>0.

公开(公告)号：US20170309344A1

公开(公告)日：2017-10-26

申请号：US15640563

申请日：2017-07-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Deepanshu Dutta ,  Arash Hazeghi ,  Huai-Yuan Tseng ,  Cynthia Hsu ,  Navneeth Kankani

IPC: G11C16/34 ,  G11C16/32 ,  G11C16/04

CPC classification number: G11C16/3459 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/32

Abstract: Systems and methods for improving the reliability of data stored in memory cells are described. To mitigate the effects of trapped electrons after one or more programming pulses have been applied to memory cells, a delay between the one or more programming pulses and subsequent program verify pulses may be set based on a chip temperature, the number of the one or more programming pulses that were applied to the memory cells, and/or the programming voltage that was applied to the memory cells during the one or more programming pulses. To mitigate the effects of residual electrons after one or more program verify pulses have been applied to memory cells, a delay between the one or more program verify pulses and subsequent programming pulses may be set based on a chip temperature and/or the programming voltage to be applied to the memory cells during the subsequent programming pulses.

公开(公告)号：US11587630B2

公开(公告)日：2023-02-21

申请号：US17206865

申请日：2021-03-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Cynthia Hsu ,  Fanglin Zhang

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10

Abstract: A data storage system includes a storage medium including a plurality of strings of single-level cell (SLC) memory cells connected to a plurality of word lines; and a storage controller in communication with the storage medium, the storage controller including write circuitry configured to write data to the storage medium by: selecting a first word line of the plurality of word lines, the first word line being connected to a first plurality of strings; consecutively programming a first group of memory cells of the first plurality of strings connected to the first word line; and subsequent to programming the first group of memory cells, consecutively verifying respective programming results of the first group of memory cells.

公开(公告)号：US20220301644A1

公开(公告)日：2022-09-22

申请号：US17206865

申请日：2021-03-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Cynthia Hsu ,  Fanglin Zhang

IPC: G11C16/34 ,  G11C16/10

Abstract: A data storage system includes a storage medium including a plurality of strings of single-level cell (SLC) memory cells connected to a plurality of word lines; and a storage controller in communication with the storage medium, the storage controller including write circuitry configured to write data to the storage medium by: selecting a first word line of the plurality of word lines, the first word line being connected to a first plurality of strings; consecutively programming a first group of memory cells of the first plurality of strings connected to the first word line; and subsequent to programming the first group of memory cells, consecutively verifying respective programming results of the first group of memory cells.

公开(公告)号：US20190035480A1

公开(公告)日：2019-01-31

申请号：US15699513

申请日：2017-09-08

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Anubhav Khandelwal ,  Changyuan Chen ,  Cynthia Hsu ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/26 ,  G11C11/56 ,  G11C16/24 ,  G11C16/04

Abstract: Non-volatile storage systems and method of operating non-volatile storage systems are disclosed. A crept up voltage on a memory cell control gate adjacent to a select gate is prevented, reduced, and/or discharged. In some aspects, the crept up voltage is not allowed to happen on the memory cell next to the select gate after a sensing operation. In some aspects, the voltage may creep up on the memory cell control gate after a sensing operation, but it is discharged. Reducing and/or preventing the crept up voltage may reduce the electric field between the dummy memory cell and select gate transistor. This may prevent, or at least reduce, changes in threshold voltage of the select gate transistor. Additional problems may also be solved by a reduction of the crept up voltage on the dummy memory cell control gates.

公开(公告)号：US10026492B2

公开(公告)日：2018-07-17

申请号：US15640563

申请日：2017-07-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Deepanshu Dutta ,  Arash Hazeghi ,  Huai-Yuan Tseng ,  Cynthia Hsu ,  Navneeth Kankani

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/32

Abstract: Systems and methods for improving the reliability of data stored in memory cells are described. To mitigate the effects of trapped electrons after one or more programming pulses have been applied to memory cells, a delay between the one or more programming pulses and subsequent program verify pulses may be set based on a chip temperature, the number of the one or more programming pulses that were applied to the memory cells, and/or the programming voltage that was applied to the memory cells during the one or more programming pulses. To mitigate the effects of residual electrons after one or more program verify pulses have been applied to memory cells, a delay between the one or more program verify pulses and subsequent programming pulses may be set based on a chip temperature and/or the programming voltage to be applied to the memory cells during the subsequent programming pulses.

公开(公告)号：US20210327520A1

公开(公告)日：2021-10-21

申请号：US16854030

申请日：2020-04-21

Applicant: SanDisk Technologies LLC

Inventor： Xue Pitner ,  Deepanshu Dutta ,  Huai-Yuan Tseng ,  Ravi Kumar ,  Cynthia Hsu

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C16/08

Abstract: A storage device is disclosed herein. The storage device comprises a block including a plurality of memory cells and a circuit coupled to the plurality of memory cells of the block. The circuit is configured to program memory cells of a plurality of strings of a word line of the block and verify, for a plurality of sets of the memory cells, a data state of a set of the memory cells, where each set of the plurality of sets of the memory cells includes a memory cell from each string of the plurality of strings of the word line. Further, the circuit is configured to determine a number of sets of the plurality of memory cell sets that are verified to be in a first data state and determine, based on the number of sets, whether the block is faulty.

公开(公告)号：US10204689B1

公开(公告)日：2019-02-12

申请号：US15699513

申请日：2017-09-08

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Anubhav Khandelwal ,  Changyuan Chen ,  Cynthia Hsu ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  G11C11/56

Abstract: Non-volatile storage systems and method of operating non-volatile storage systems are disclosed. A crept up voltage on a memory cell control gate adjacent to a select gate is prevented, reduced, and/or discharged. In some aspects, the crept up voltage is not allowed to happen on the memory cell next to the select gate after a sensing operation. In some aspects, the voltage may creep up on the memory cell control gate after a sensing operation, but it is discharged. Reducing and/or preventing the crept up voltage may reduce the electric field between the dummy memory cell and select gate transistor. This may prevent, or at least reduce, changes in threshold voltage of the select gate transistor. Additional problems may also be solved by a reduction of the crept up voltage on the dummy memory cell control gates.

公开(公告)号：US09881676B1

公开(公告)日：2018-01-30

申请号：US15290818

申请日：2016-10-11

Applicant: SanDisk Technologies LLC

Inventor： Jong Hak Yuh ,  Raul Adrian Cernea ,  Seungpil Lee ,  Yen-Lung Jason Li ,  Qui Nguyen ,  Tai-Yuan Tseng ,  Cynthia Hsu

IPC: G11C7/10 ,  G11C16/12 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24

CPC classification number: G11C16/12 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

Abstract: Apparatuses, systems, and methods are disclosed for accessing non-volatile memory. A bit line is coupled to storage cells for a non-volatile memory element. A sense amplifier is coupled to a bit line. A sense amplifier includes a sense circuit and a bias circuit. A sense circuit senses an electrical property of a bit line for reading data from one or more storage cells, and a bias circuit applies a bias voltage to the bit line for writing data to one or more storage cells. A bias circuit and a sense circuit comprise separate parallel electrical paths within a sense amplifier.

公开(公告)号：US11302409B2

公开(公告)日：2022-04-12

申请号：US16854030

申请日：2020-04-21

Applicant: SanDisk Technologies LLC

Inventor： Xue Pitner ,  Deepanshu Dutta ,  Huai-Yuan Tseng ,  Ravi Kumar ,  Cynthia Hsu

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

Abstract: A storage device is disclosed herein. The storage device comprises a block including a plurality of memory cells and a circuit coupled to the plurality of memory cells of the block. The circuit is configured to program memory cells of a plurality of strings of a word line of the block and verify, for a plurality of sets of the memory cells, a data state of a set of the memory cells, where each set of the plurality of sets of the memory cells includes a memory cell from each string of the plurality of strings of the word line. Further, the circuit is configured to determine a number of sets of the plurality of memory cell sets that are verified to be in a first data state and determine, based on the number of sets, whether the block is faulty.