公开(公告)号：US20190187553A1

公开(公告)日：2019-06-20

申请号：US15845456

申请日：2017-12-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel J. Linnen ,  Jianhua Zhu ,  Srikar Peesari ,  Kirubakaran Periyannan ,  Avinash Rajagiri ,  Shantanu Gupta ,  Jagdish Sabde ,  Ashish Ghai ,  Deepak Bharadwaj

IPC: G03F1/50

CPC classification number: G03F1/50

Abstract: An apparatus is provided that includes a reticle including a die, the reticle configured to increase a number of partial die that can be successfully used as partially operable die.

公开(公告)号：US10776277B2

公开(公告)日：2020-09-15

申请号：US15799643

申请日：2017-10-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel Linnen ,  Srikar Peesari ,  Kirubakaran Periyannan ,  Avinash Rajagiri ,  Shantanu Gupta ,  Jagdish Sabde ,  Ashish Ghai ,  Deepak Bharadwaj

IPC: G06F12/10 ,  G06F3/06 ,  G11C16/04 ,  G11C13/00 ,  G11C11/16 ,  G11C16/08 ,  G11C5/02 ,  G11C16/10 ,  G11C8/06 ,  G11C7/10

Abstract: A partial memory die comprises a memory structure that includes a first plane of non-volatile memory cells and a second plane of non-volatile memory cells. The second plane of non-volatile memory cells is incomplete. A first buffer is connected to the first plane. A second buffer is connected to the second plane. A data path circuit is connected to an input interface, the first buffer and the second buffer. The data path circuit is configured to map data received at the input interface and route the mapped data to either the first buffer or the second buffer. An inter-plane re-mapping circuit is connected to the first buffer and the second buffer, and is configured to re-map data from the first buffer and store the re-mapped data in the second buffer for programming into the second plane.

公开(公告)号：US20190130978A1

公开(公告)日：2019-05-02

申请号：US15799666

申请日：2017-10-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel Linnen ,  Srikar Peesari ,  Kirubakaran Periyannan ,  Avinash Rajagiri ,  Shantanu Gupta ,  Jagdish Sabde ,  Ashish Ghai ,  Deepak Bharadwaj ,  Sukhminder Singh Lobana ,  Shrikar Bhagath

IPC: G11C16/10 ,  G11C16/04 ,  H01L27/11529 ,  H01L27/11573

Abstract: A partial memory die is missing one or more components. One example of a partial memory die includes an incomplete memory structure such that the partial memory die is configured to successfully perform programming, erasing and reading of the incomplete memory structure.

公开(公告)号：US20190129861A1

公开(公告)日：2019-05-02

申请号：US15799643

申请日：2017-10-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel Linnen ,  Srikar Peesari ,  Kirubakaran Periyannan ,  Avinash Rajagiri ,  Shantanu Gupta ,  Jagdish Sabde ,  Ashish Ghai ,  Deepak Bharadwaj

IPC: G06F12/10 ,  G06F3/06 ,  G11C16/04 ,  G11C13/00 ,  G11C11/16

CPC classification number: G06F12/10 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0679 ,  G06F2212/1044 ,  G06F2212/2022 ,  G06F2212/657 ,  G11C5/02 ,  G11C7/1039 ,  G11C8/06 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0069 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C2207/107

Abstract: A partial memory die comprises a memory structure that includes a first plane of non-volatile memory cells and a second plane of non-volatile memory cells. The second plane of non-volatile memory cells is incomplete. A first buffer is connected to the first plane. A second buffer is connected to the second plane. A data path circuit is connected to an input interface, the first buffer and the second buffer. The data path circuit is configured to map data received at the input interface and route the mapped data to either the first buffer or the second buffer. An inter-plane re-mapping circuit is connected to the first buffer and the second buffer, and is configured to re-map data from the first buffer and store the re-mapped data in the second buffer for programming into the second plane.

公开(公告)号：US10290354B1

公开(公告)日：2019-05-14

申请号：US15799666

申请日：2017-10-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel Linnen ,  Srikar Peesari ,  Kirubakaran Periyannan ,  Avinash Rajagiri ,  Shantanu Gupta ,  Jagdish Sabde ,  Ashish Ghai ,  Deepak Bharadwaj ,  Sukhminder Singh Lobana ,  Shrikar Bhagath

IPC: G11C5/06 ,  G11C16/10 ,  H01L27/11573 ,  H01L27/11529 ,  G11C16/04

Abstract: A partial memory die is missing one or more components. One example of a partial memory die includes an incomplete memory structure such that the partial memory die is configured to successfully perform programming, erasing and reading of the incomplete memory structure.