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1.发明授权公开(公告)号：US10921840B2
公开(公告)日：2021-02-16
申请号：US16673289
申请日：2019-11-04
Applicant: SK hynix Inc.
Inventor： Tae Jin Hwang
IPC: G05F3/26
Abstract: A voltage generator includes a bias voltage generation circuit and a compensation circuit. The bias voltage generation circuit generates a first bias voltage based on a reference current and generates a second bias voltage based on the first bias voltage. The compensation circuit changes a voltage level of the first bias voltage based on the second bias voltage.
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2.发明授权公开(公告)号：US09317052B1
公开(公告)日：2016-04-19
申请号：US14552141
申请日：2014-11-24
Applicant: SK hynix Inc.
Inventor： Tae Jin Hwang
CPC classification number: G05F1/468
Abstract: A calibration circuit of a semiconductor apparatus may include: a reference voltage generator suitable for generating first and second pull-up reference voltages based on a pull-up control signal, and generating first and second pull-down reference voltages based on a pull-down control signal; and a calibrator suitable for generating a pull-up resistor code corresponding to an external reference resistor based on the first and second pull-up reference voltages, and generating a pull-down resistor code corresponding to the external reference resistor based on the first and second pull-down reference voltages and the pull-up resistor code.
Abstract translation: 半导体装置的校准电路可以包括：参考电压发生器，其适于基于上拉控制信号产生第一和第二上拉参考电压，以及基于下拉电平产生第一和第二下拉参考电压 控制信号; 以及校准器，其适于基于所述第一和第二上拉参考电压产生对应于外部参考电阻器的上拉电阻器代码，并且基于所述第一和第二上拉电压产生对应于所述外部参考电阻器的下拉电阻器代码 下拉参考电压和上拉电阻代码。
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公开(公告)号：US09190372B2
公开(公告)日：2015-11-17
申请号：US14550328
申请日：2014-11-21
Applicant: SK hynix Inc.
Inventor： Chang Kun Park , Seong Hwi Song , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang
IPC: H01L27/10 , H01L23/00 , H01L23/528 , H01L27/105
CPC classification number: H01L24/06 , H01L23/5286 , H01L24/09 , H01L27/1052 , H01L2224/061 , H01L2224/0612 , H01L2224/06515 , H01L2224/091 , H01L2224/09515 , H01L2924/14 , H01L2924/1434 , H01L2924/30101 , H01L2924/3011 , H01L2924/00
Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.
Abstract translation: 半导体存储器件包括具有芯片焊盘形成区域的半导体电路基板。 在芯片焊盘区域一侧的半导体电路基板上形成一对数据线。 一对数据线沿着半导体电路基板的芯片焊盘区域延伸的方向延伸。 这对数据线被布置为彼此相邻并且接收一对差分数据信号。 电源线形成在芯片焊盘区域的另一侧的半导体电路基板上。 电源线沿着半导体电路基板的芯片焊盘区域延伸的方向延伸，并且电源线接收电力。
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公开(公告)号：US09041447B2
公开(公告)日：2015-05-26
申请号：US13720424
申请日：2012-12-19
Applicant: SK hynix Inc.
Inventor： Tae Jin Hwang
CPC classification number: H03K5/02 , H03F3/45076 , H03K2005/00013 , H04L25/0292 , H04L25/03878 , H04L27/01
Abstract: A receiver circuit includes a first amplification unit, a second amplification unit, a first equalizing unit, and a second equalizing unit. The first amplification unit is configured to differentially amplify an input signal and a reference signal and generate a first intermediate output signal and a second intermediate output signal. The second amplification unit is configured to differentially amplify the first and second intermediate output signals and generate an output signal. The first equalizing unit is configured to control the level of the second intermediate output signal in response to the output signal. And the second equalizing unit is configured to control the level of the first intermediate output signal in response to the output signal.
Abstract translation: 接收机电路包括第一放大单元，第二放大单元，第一均衡单元和第二均衡单元。 第一放大单元被配置为差分放大输入信号和参考信号，并产生第一中间输出信号和第二中间输出信号。 第二放大单元被配置为差分放大第一和第二中间输出信号并产生输出信号。 第一均衡单元被配置为响应于输出信号来控制第二中间输出信号的电平。 并且第二均衡单元被配置为响应于输出信号来控制第一中间输出信号的电平。
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公开(公告)号：US20220069813A1
公开(公告)日：2022-03-03
申请号：US17171719
申请日：2021-02-09
Applicant: SK hynix Inc.
Inventor： Sun Ki Cho , Dong Uc Ko , Yang Ho Sur , Jun Yong Song , Sung Gil Jang , Hae Kang Jung , Min Sung Cheon , Chang Kyu Choi , Tae Jin Hwang
Abstract: A buffer circuit configured to receive first and second input signals through first and second input transistors coupled to a first power voltage node, output a first output signal through a first output node and a second output signal through a second output node based on the first and second input signals. A load circuit is coupled among the first output node, the second output node, and a second power voltage node and a resistance value is adjusted based on at least one of the first and second output signals.
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Patent Agency Ranking
公开(公告)号：US10284156B2
公开(公告)日：2019-05-07
申请号：US15668097
申请日：2017-08-03
Applicant: SK hynix Inc.
Inventor： Dong Hyun Kim , Eun Ji Choi , Yo Han Jeong , Soon Ku Kang , Woo Jin Kang , Kwan Su Shon , Hyun Bae Lee , Tae Jin Hwang
Abstract: An amplifier may include a differential pair circuit configured to generate an output signal according to a first input signal and a second input signal, a plurality of current sinks coupled between a ground terminal and the differential pair circuit, and a feedback circuit configured to sense a level of the output signal and generate a feedback signal. At least one of the plurality of current sinks is controlled according to the feedback signal.
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公开(公告)号：US09595498B2
公开(公告)日：2017-03-14
申请号：US14960716
申请日：2015-12-07
Applicant: SK hynix Inc.
Inventor： Chang Kun Park , Seong Hwi Song , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang
IPC: H01L23/52 , H01L23/00 , H01L23/528 , H01L27/105
CPC classification number: H01L24/06 , H01L23/5286 , H01L24/09 , H01L27/1052 , H01L2224/061 , H01L2224/0612 , H01L2224/06515 , H01L2224/091 , H01L2224/09515 , H01L2924/14 , H01L2924/1434 , H01L2924/30101 , H01L2924/3011 , H01L2924/00
Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.
Abstract translation: 半导体存储器件包括具有芯片焊盘形成区域的半导体电路基板。 在芯片焊盘区域一侧的半导体电路基板上形成一对数据线。 一对数据线沿着半导体电路基板的芯片焊盘区域延伸的方向延伸。 这对数据线被布置为彼此相邻并且接收一对差分数据信号。 电源线形成在芯片焊盘区域的另一侧的半导体电路基板上。 电源线沿着半导体电路基板的芯片焊盘区域延伸的方向延伸，并且电源线接收电力。
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公开(公告)号：US09479170B2
公开(公告)日：2016-10-25
申请号：US14550544
申请日：2014-11-21
Applicant: SK hynix Inc.
Inventor： Tae Jin Hwang
IPC: H03K19/003
CPC classification number: H03K19/00384
Abstract: A buffer circuit includes an amplification unit suitable for sensing and amplifying an input signal and a reference voltage, a buffer enable unit suitable for enabling the amplification unit based on a buffer enable signal, and a buffer enable signal generation unit suitable for generating the buffer enable signal based on a first or second operation control signal, selected according to a high voltage detection signal.
Abstract translation: 缓冲电路包括适于感测和放大输入信号和参考电压的放大单元，适用于基于缓冲器使能信号使得放大单元能够使能的缓冲器使能单元和适于产生缓冲器使能的缓冲器使能信号生成单元 基于根据高电压检测信号选择的第一或第二操作控制信号的信号。
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公开(公告)号：US09209145B2
公开(公告)日：2015-12-08
申请号：US14550445
申请日：2014-11-21
Applicant: SK hynix Inc.
Inventor： Chang Kun Park , Seong Hwi Song , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang
IPC: H01L27/10 , H01L23/00 , H01L23/528 , H01L27/105
CPC classification number: H01L24/06 , H01L23/5286 , H01L24/09 , H01L27/1052 , H01L2224/061 , H01L2224/0612 , H01L2224/06515 , H01L2224/091 , H01L2224/09515 , H01L2924/14 , H01L2924/1434 , H01L2924/30101 , H01L2924/3011 , H01L2924/00
Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.
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公开(公告)号：US11271553B1
公开(公告)日：2022-03-08
申请号：US17171719
申请日：2021-02-09
Applicant: SK hynix Inc.
Inventor： Sun Ki Cho , Dong Uc Ko , Yang Ho Sur , Jun Yong Song , Sung Gil Jang , Hae Kang Jung , Min Sung Cheon , Chang Kyu Choi , Tae Jin Hwang
Abstract: A buffer circuit configured to receive first and second input signals through first and second input transistors coupled to a first power voltage node, output a first output signal through a first output node and a second output signal through a second output node based on the first and second input signals. A load circuit is coupled among the first output node, the second output node, and a second power voltage node and a resistance value is adjusted based on at least one of the first and second output signals.
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