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公开(公告)号:US12101080B2
公开(公告)日:2024-09-24
申请号:US18302440
申请日:2023-04-18
Applicant: Soitec
Inventor: Arnaud Castex , Daniel Delprat , Bernard Aspar , Ionut Radu
IPC: H03H9/02 , H03H3/04 , H03H3/10 , H03H9/64 , H10N30/00 , H10N30/072 , H10N30/073 , H10N30/082 , H10N30/086 , H10N30/853 , H10N35/01
CPC classification number: H03H9/02834 , H03H3/04 , H03H3/10 , H03H9/02574 , H10N30/072 , H10N30/073 , H10N30/704 , H10N30/8542 , H03H9/6496 , H10N30/082 , H10N30/086 , H10N35/01 , Y10T29/42
Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.
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公开(公告)号:US20180159498A1
公开(公告)日:2018-06-07
申请号:US15735477
申请日:2016-06-09
Applicant: Soitec
Inventor: Arnaud Castex , Daniel Delprat , Bernard Aspar , Ionut Radu
Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.
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3.
公开(公告)号:US08790993B2
公开(公告)日:2014-07-29
申请号:US13953679
申请日:2013-07-29
Applicant: SOITEC
Inventor: Sebastien Kerdiles , Daniel Delprat
CPC classification number: H01L21/67132 , H01L21/02 , H01L21/187 , H01L21/76251
Abstract: A method for bonding a first substrate having a first surface to a second substrate having a second surface. This method includes the steps of holding the first substrate by at least two support points, positioning the first substrate and the second substrate so that the first surface and the second surface face each other, deforming the first substrate by applying between at least one pressure point and the two support points a strain toward the second substrate, bringing the deformed first surface and the second surface into contact, and progressively releasing the strain to facilitate bonding of the substrates while minimizing or avoiding the trapping of air bubbles between the substrates.
Abstract translation: 一种用于将具有第一表面的第一基底结合到具有第二表面的第二基底的方法。 该方法包括以下步骤:通过至少两个支撑点保持第一基板,将第一基板和第二基板定位成使得第一表面和第二表面彼此面对,使第一基板通过在至少一个压力点 并且两个支撑点朝向第二基板的应变,使变形的第一表面和第二表面接触,并逐渐释放应变以促进基板的接合,同时最小化或避免在基板之间捕获气泡。
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公开(公告)号:US20230275559A1
公开(公告)日:2023-08-31
申请号:US18302440
申请日:2023-04-18
Applicant: Soitec
Inventor: Arnaud Castex , Daniel Delprat , Bernard Aspar , Ionut Radu
IPC: H03H9/02 , H03H3/04 , H10N30/072 , H10N30/073 , H10N30/00 , H10N30/853 , H03H3/10
CPC classification number: H03H9/02834 , H03H9/02574 , H03H3/04 , H10N30/072 , H10N30/073 , H10N30/1051 , H10N30/8542 , H03H3/10 , Y10T29/42 , H10N30/082
Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.
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公开(公告)号:US20200280298A1
公开(公告)日:2020-09-03
申请号:US16877309
申请日:2020-05-18
Applicant: Soitec
Inventor: Arnaud Castex , Daniel Delprat , Bernard Aspar , Ionut Radu
IPC: H03H9/02 , H01L41/312 , H01L41/08 , H01L41/313 , H03H3/10
Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.
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6.
公开(公告)号:US20130309841A1
公开(公告)日:2013-11-21
申请号:US13953679
申请日:2013-07-29
Applicant: SOITEC
Inventor: Sebastien Kerdiles , Daniel Delprat
IPC: H01L21/02
CPC classification number: H01L21/67132 , H01L21/02 , H01L21/187 , H01L21/76251
Abstract: The present invention concerns a method for bonding a first substrate having a first surface to a second substrate having a second surface. This method includes the steps of holding the first substrate by at least two support points, positioning the first substrate and the second substrate so that the first surface and the second surface face each other, deforming the first substrate by applying between at least one pressure point and the two support points a strain toward the second substrate, bringing the deformed first surface and the second surface into contact, and progressively releasing the strain to facilitate bonding of the substrates while minimizing or avoiding the trapping of air bubbles between the substrates.
Abstract translation: 本发明涉及一种用于将具有第一表面的第一衬底与具有第二表面的第二衬底结合的方法。 该方法包括以下步骤:通过至少两个支撑点保持第一基板,将第一基板和第二基板定位成使得第一表面和第二表面彼此面对,使第一基板通过在至少一个压力点 并且两个支撑点朝向第二基板的应变,使变形的第一表面和第二表面接触,并逐渐释放应变以促进基板的接合,同时最小化或避免在基板之间捕获气泡。
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公开(公告)号:US20240396520A1
公开(公告)日:2024-11-28
申请号:US18790454
申请日:2024-07-31
Applicant: Soitec
Inventor: Arnaud Castex , Daniel Delprat , Bernard Aspar , Ionut Radu
IPC: H03H9/02 , H03H3/04 , H03H3/10 , H03H9/64 , H10N30/072 , H10N30/073 , H10N30/082 , H10N30/086 , H10N30/853 , H10N35/01
Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.
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公开(公告)号:US11637542B2
公开(公告)日:2023-04-25
申请号:US17075465
申请日:2020-10-20
Applicant: Soitec
Inventor: Arnaud Castex , Daniel Delprat , Bernard Aspar , Ionut Radu
IPC: H03H9/02 , H01L41/08 , H03H3/04 , H03H9/64 , H01L41/312 , H01L41/313 , H01L41/187 , H03H3/10 , H01L41/47 , H01L41/332 , H01L41/337
Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.
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公开(公告)号:US20230005787A1
公开(公告)日:2023-01-05
申请号:US17756244
申请日:2020-11-25
Applicant: Soitec
Inventor: Young-Pil Kim , Daniel Delprat , Luciana Capello , Isabelle Bertrand , Frédéric Allibert
IPC: H01L21/762 , H01L23/66 , H01L27/12 , H01L21/02
Abstract: A handle substrate for a composite structure comprises a base substrate including an epitaxial layer of silicon on a monocrystalline silicon wafer obtained by Czochralski pulling, a passivation layer on and in contact with the epitaxial layer of silicon, and a charge-trapping layer on and in contact with the passivation layer. The monocrystalline silicon wafer of the base substrate exhibits a resistivity of between 10 and 500 ohm·cm, while the epitaxial layer of silicon exhibits a resistivity of greater than 2000 ohm·cm and a thickness ranging from 2 to 100 microns. The passivation layer is amorphous or polycrystalline. A method is described for forming such a substrate.
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公开(公告)号:US20210050250A1
公开(公告)日:2021-02-18
申请号:US16969350
申请日:2019-02-12
Applicant: Soitec
Inventor: Daniel Delprat , Damien Parissi , Marcel Broekaart
IPC: H01L21/762 , H01L21/02
Abstract: A method for manufacturing a semiconductor on insulator type structure by transfer of a layer from a donor substrate onto a receiver substrate, comprises: a) the supply of the donor substrate and the receiver substrate, b) the formation in the donor substrate of an embrittlement zone delimiting the layer to transfer, c) the bonding of the donor substrate on the receiver substrate, the surface of the donor substrate opposite to the embrittlement zone with respect to the layer to transfer being at the bonding interface, and d) the detachment of the donor substrate along the embrittlement zone. A step of controlled modification of the curvature of the donor substrate and/or the receiver substrate is performed before the bonding step.
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