公开(公告)号：US20230099610A1

公开(公告)日：2023-03-30

申请号：US18061795

申请日：2022-12-05

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Edoardo ZANETTI ,  Simone RASCUNA' ,  Mario Giuseppe SAGGIO ,  Alfio GUARNERA ,  Leonardo FRAGAPANE ,  Cristina TRINGALI

IPC: H01L21/04 ,  H01L21/285 ,  H01L29/872 ,  H01L29/66 ,  H01L29/16 ,  H01L29/78 ,  H01L29/06

Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.

公开(公告)号：US20190172715A1

公开(公告)日：2019-06-06

申请号：US16209680

申请日：2018-12-04

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Edoardo ZANETTI ,  Simone RASCUNÁ ,  Mario Giuseppe SAGGIO ,  Alfio GUARNERA ,  Leonardo FRAGAPANE ,  Cristina TRINGALI

IPC: H01L21/04 ,  H01L21/285 ,  H01L29/66 ,  H01L29/16 ,  H01L29/872

Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.

公开(公告)号：US20150372075A1

公开(公告)日：2015-12-24

申请号：US14666013

申请日：2015-03-23

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Leonardo FRAGAPANE

IPC: H01L29/06 ,  H01L21/761 ,  H01L21/266 ,  H01L29/16

CPC classification number: H01L29/063 ,  H01L21/0415 ,  H01L21/266 ,  H01L21/761 ,  H01L21/8213 ,  H01L29/0615 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/7393 ,  H01L29/7802 ,  H01L29/7816 ,  H01L29/8611

Abstract: An integrated device has: a structural layer of semiconductor material doped with a first conductivity type and having a top surface defining a plane; a functional region, doped with a second conductivity type, arranged in an active area of the structural layer at the top surface, in the proximity of an edge area of the integrated device, which externally surrounds the active area; and an edge termination region, doped with the second conductivity type, joined to the functional region and arranged in the edge area. The edge termination region has a doping profile and a junction depth that vary in a first direction parallel to the plane.

Abstract translation: 集成器件具有：掺杂有第一导电类型且具有限定平面的顶表面的半导体材料的结构层; 掺杂有第二导电类型的功能区域，其布置在所述结构层的顶表面的有源区域中，所述功能区域在所述集成器件的边缘区域附近，所述边缘区域在外部围绕所述有源区域; 并且掺杂有第二导电类型的边缘终止区域连接到功能区域并且布置在边缘区域中。 边缘终端区域具有在平行于平面的第一方向上变化的掺杂分布和结深度。

公开(公告)号：US20240170568A1

公开(公告)日：2024-05-23

申请号：US18506777

申请日：2023-11-10

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Leonardo FRAGAPANE

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7811 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/66068 ,  H01L29/7823

Abstract: An integrated device includes: a semiconductor structural layer, including silicon carbide and having a first conductivity type; a power device integrated in the structural layer; and an edge termination structure, extending in a ring around the power device and having a second conductivity type. The edge termination structure includes a plurality of ring structures each arranged around the power device and in contiguous pairs. At least a first one of the ring structures comprises a transition region contiguous to a second one of the ring structures. The transition region includes connection regions, having the second conductivity type, connected to the second one of the ring structures and alternating with charge control regions having the first conductivity type.

公开(公告)号：US20140138739A1

公开(公告)日：2014-05-22

申请号：US14166075

申请日：2014-01-28

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Angelo MAGRI' ,  Antonino Sebastiano ALESSANDRIA ,  Stefania FORTUNA ,  Leonardo FRAGAPANE

IPC: H01L29/10 ,  H01L29/739

CPC classification number: H01L29/1037 ,  H01L29/405 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/4941 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

Abstract: An embodiment of a method for manufacturing a power device being integrated on a semiconductor substrate comprising at least the steps of making, in the semiconductor substrate, at least a trench having sidewalls and a bottom, covering the sidewalls and the bottom of said at least one trench with a first insulating coating layer and making, inside said at least one trench, a conductive gate structure. An embodiment of the method provides the formation of the conductive gate structure comprising the steps of covering at least the sidewalls with a second conductive coating layer of a first conductive material; making a conductive central region of a second conductive material having a different resistivity than the first conductive material; and making a plurality of conductive bridges between said second conductive coating layer and said conductive central region.

Abstract translation: 一种用于制造集成在半导体衬底上的功率器件的方法的实施例，至少包括以下步骤：在半导体衬底中至少形成具有侧壁和底部的沟槽，覆盖所述至少一个的侧壁和底部 沟槽，其具有第一绝缘涂层并且在所述至少一个沟槽内部形成导电栅极结构。 该方法的一个实施例提供了导电栅极结构的形成，包括以下步骤：用第一导电材料的第二导电涂层覆盖至少侧壁; 制造具有与第一导电材料不同的电阻率的第二导电材料的导电中心区域; 以及在所述第二导电涂层和所述导电中心区之间形成多个导电桥。

公开(公告)号：US20240162040A1

公开(公告)日：2024-05-16

申请号：US18509043

申请日：2023-11-14

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Edoardo ZANETTI ,  Simone RASCUNA' ,  Mario Giuseppe SAGGIO ,  Alfio GUARNERA ,  Leonardo FRAGAPANE ,  Cristina TRINGALI

IPC: H01L21/04 ,  H01L21/285 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/872

CPC classification number: H01L21/046 ,  H01L21/0495 ,  H01L21/28537 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872 ,  H01L29/8725

Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.

公开(公告)号：US20240113179A1

公开(公告)日：2024-04-04

申请号：US18471219

申请日：2023-09-20

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Laura Letizia SCALIA ,  Cateno Marco CAMALLERI ,  Leonardo FRAGAPANE

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41741 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/1608 ,  H01L29/401 ,  H01L29/66068 ,  H01L29/7802

Abstract: Electronic device, comprising: a semiconductor body having a surface; a body region in the semiconductor body, extending along a main direction parallel to the surface of the semiconductor body; and a source region in the body region, extending along the main direction. The electronic device has, at the body and source regions, a first and a second electrical contact region alternating with each other along the main direction, wherein the first electrical contact region exposes the body region, and the second electrical contact region exposes the source region. The electronic device further comprises an electrical connection layer extending with electrical continuity longitudinally to the body and source regions, in electrical connection with the first and the second electrical contact regions.

公开(公告)号：US20210249268A1

公开(公告)日：2021-08-12

申请号：US17244393

申请日：2021-04-29

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Edoardo ZANETTI ,  Simone RASCUNA' ,  Mario Giuseppe SAGGIO ,  Alfio GUARNERA ,  Leonardo FRAGAPANE ,  Cristina TRINGALI

IPC: H01L21/04 ,  H01L21/285 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/16 ,  H01L29/872

Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.