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    FeFET transistor
    3.
    发明授权
    FeFET transistor 有权

    公开(公告)号：US11677024B2

    公开(公告)日：2023-06-13

    申请号：US17323545

    申请日：2021-05-18

    Applicant: STMicroelectronics (Crolles 2) SAS

    Inventor： Mickael Gros-Jean ,  Julien Ferrand

    IPC: H01L29/78 ,  H01L21/28 ,  H01L27/07 ,  H01L29/51 ,  H01L29/66

    CPC classification number: H01L29/78391 ,  H01L27/0705 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/517 ,  H01L29/6684

    Abstract: A method for manufacturing first and second transistors on a semiconductor substrate includes: depositing an interface layer on the semiconductor substrate; depositing a gate insulator layer on the interface layer; depositing a first ferroelectric layer on the gate insulator layer over a first region for the first transistor; depositing a metal gate layer on the gate insulator layer over a second region for the second transistor and on the first ferroelectric layer over the first region for the first transistor; and patterning the metal gate layer, first ferroelectric layer, gate insulator layer and interface layer to form a first gate stack for the first transistor which includes the metal gate layer, first ferroelectric layer, gate insulator layer and interface layer and a second gate stack for the second transistor which includes the metal gate layer, gate insulator layer and interface layer.

    Optoelectronic device, in particular memory device
    4.
    发明授权
    Optoelectronic device, in particular memory device 有权
    光电器件，特别是存储器件

    公开(公告)号：US09536599B1

    公开(公告)日：2017-01-03

    申请号：US15249583

    申请日：2016-08-29

    Applicant: STMICROELECTRONICS (CROLLES 2) SAS

    Inventor： Pierre Caubet ,  Mickael Gros-Jean

    IPC: G11C7/00 ,  G11C11/42 ,  G11C13/04 ,  G02F1/15

    CPC classification number: G11C11/42 ,  G02F1/15 ,  G02F1/1523 ,  G02F1/1525 ,  G02F1/1527 ,  G02F1/163 ,  G02F3/022 ,  G02F2001/1512 ,  G02F2001/1635 ,  G02F2201/58 ,  G11C7/00 ,  G11C13/04

    Abstract: A memory device may include an access transistor, and a memory cell configured to store an item of information. The memory cell may include first and second electrodes configured to have different optoelectronic states corresponding respectively to two values of the item of information, and to switch between the different optoelectronic states based upon a control signal external to the memory cell, the different optoelectronic states being naturally stable in an absence of the control signal. The memory cell may also include a solid electrolyte between the first and second electrodes.

    Abstract translation: 存储器件可以包括存取晶体管，以及被配置为存储信息项的存储单元。 存储单元可以包括被配置为具有分别对应于信息项的两个值的不同光电子状态的第一和第二电极，以及基于存储单元外部的控制信号在不同的光电子态之间切换，不同的光电子态是 在没有控制信号的情况下自然稳定。 存储单元还可以包括在第一和第二电极之间的固体电解质。

    BACK-ILLUMINATED INTEGRATED IMAGING DEVICE WITH SIMPLIFIED INTERCONNECT ROUTING
    5.
    发明申请
    BACK-ILLUMINATED INTEGRATED IMAGING DEVICE WITH SIMPLIFIED INTERCONNECT ROUTING 有权
    具有简化的互连路由的后置照明集成成像装置

    公开(公告)号：US20160099278A1

    公开(公告)日：2016-04-07

    申请号：US14847391

    申请日：2015-09-08

    Applicant: STMicroelectronics (Crolles 2) SAS

    Inventor： Francois Guyader ,  Jean-Pierre Oddou ,  Stephane Allegret-Maret ,  Mickael Gros-Jean

    IPC: H01L27/146

    CPC classification number: H01L27/14636 ,  H01L27/1203 ,  H01L27/1462 ,  H01L27/14623 ,  H01L27/14629 ,  H01L27/1463 ,  H01L27/1464

    Abstract: A back-illuminated integrated imaging device is formed from a semiconductor substrate including a zone of pixels bounded by capacitive deep trench isolations. A peripheral zone is located outside the zone of pixels. A continuous electrically conductive layer forms, in the zone of pixels, an electrode in a trench for each capacitive deep trench isolation, and forms, in the peripheral zone, a redistribution layer for electrically coupling the electrode to a biasing contact pad. The electrode is located in the trench between a trench dielectric and at least one material for filling the trench.

    Abstract translation: 背照式集成成像装置由包括由电容深沟槽隔离限制的像素区域的半导体衬底形成。 外围区域位于像素区域之外。 连续导电层在像素区域中形成用于每个电容深沟槽隔离的沟槽中的电极，并且在周边区域中形成用于将电极电耦合到偏置接触焊盘的再分布层。 电极位于沟槽电介质和用于填充沟槽的至少一种材料之间的沟槽中。

    Method for manufacturing insulated-gate MOS transistors
    6.
    发明授权
    Method for manufacturing insulated-gate MOS transistors 有权
    绝缘栅MOS晶体管的制造方法

    公开(公告)号：US08878331B2

    公开(公告)日：2014-11-04

    申请号：US13659771

    申请日：2012-10-24

    Applicant: STMicroelectronics (Crolles 2) SAS

    Inventor： Mickael Gros-Jean ,  Clement Gaumer ,  Emmanuel Bayard Perrin

    IPC: H01L29/02 ,  H01L21/70 ,  H01L21/28 ,  H01L29/51 ,  H01L21/762 ,  H01L21/8234

    CPC classification number: H01L21/76232 ,  H01L21/28229 ,  H01L21/823481 ,  H01L29/513 ,  H01L29/518

    Abstract: A method for defining an insulator in a semiconductor substrate includes forming a trench in the substrate, forming in the trench an insulating material having its upper surface arranged above the surface of the substrate, and forming a diffusion barrier layer in a portion of the insulating material located above the surface of the semiconductor substrate. Such insulators can be used, for example, to insulate and delineate electronic components or portions of components formed in the substrate.

    Abstract translation: 一种用于在半导体衬底中限定绝缘体的方法包括在衬底中形成沟槽，在沟槽中形成其上表面布置在衬底表面上方的绝缘材料，并在绝缘材料的一部分中形成扩散阻挡层 位于半导体衬底的表面上方。 这样的绝缘体可以用于例如绝缘并描绘形成在基板中的电子部件或部件。

    Optoelectronic device, in particular memory device
    8.
    发明授权
    Optoelectronic device, in particular memory device 有权
    光电器件，特别是存储器件

    公开(公告)号：US09530489B2

    公开(公告)日：2016-12-27

    申请号：US14527166

    申请日：2014-10-29

    Applicant: STMICROELECTRONICS (CROLLES 2) SAS

    Inventor： Pierre Caubet ,  Mickael Gros-Jean

    IPC: G11C7/00 ,  G11C11/42 ,  G11C13/04 ,  G02F1/163 ,  G02F1/15 ,  G02F3/02

    CPC classification number: G11C11/42 ,  G02F1/15 ,  G02F1/1523 ,  G02F1/1525 ,  G02F1/1527 ,  G02F1/163 ,  G02F3/022 ,  G02F2001/1512 ,  G02F2001/1635 ,  G02F2201/58 ,  G11C7/00 ,  G11C13/04

    Abstract: A memory device may include an access transistor, and a memory cell configured to store an item of information. The memory cell may include first and second electrodes configured to have different optoelectronic states corresponding respectively to two values of the item of information, and to switch between the different optoelectronic states based upon a control signal external to the memory cell, the different optoelectronic states being naturally stable in an absence of the control signal. The memory cell may also include a solid electrolyte between the first and second electrodes.

    Abstract translation: 存储器件可以包括存取晶体管，以及被配置为存储信息项的存储单元。 存储单元可以包括被配置为具有分别对应于信息项的两个值的不同光电子状态的第一和第二电极，以及基于存储单元外部的控制信号在不同的光电子态之间切换，不同的光电子态是 在没有控制信号的情况下自然稳定。 存储单元还可以包括在第一和第二电极之间的固体电解质。

    METHOD FOR MANUFACTURING A POLYCRYSTALLINE DIELECTRIC LAYER
    9.
    发明申请
    METHOD FOR MANUFACTURING A POLYCRYSTALLINE DIELECTRIC LAYER 审中-公开
    制造多晶介质层的方法

    公开(公告)号：US20140021586A1

    公开(公告)日：2014-01-23

    申请号：US14036519

    申请日：2013-09-25

    Applicant: STMicroelectronics (Crolles 2) SAS

    Inventor： Mickael Gros-Jean

    IPC: H01L49/02

    CPC classification number: H01L28/40 ,  C23C16/405 ,  C23C16/45529 ,  C23C16/45542 ,  H01G4/085 ,  H01G4/1209 ,  H01G4/33 ,  H01L21/02189 ,  H01L21/02274 ,  H01L21/0228 ,  Y10T29/42 ,  Y10T29/43 ,  Y10T29/435

    Abstract: A method manufactures a capacitor having polycrystalline dielectric layer between two metallic electrodes. The dielectric layer is formed by a polycrystalline growth of a dielectric metallic oxide on one of the metallic electrodes. At least one polycrystalline growth condition of the dielectric oxide is modified during the formation of the polycrystalline dielectric layer, which results in a variation of the polycrystalline properties of the dielectric oxide within the thickness of said layer.

    Abstract translation: 一种制造在两个金属电极之间具有多晶介质层的电容器。 电介质层由金属电极之一上的介电金属氧化物的多晶生长形成。 在形成多晶电介质层期间，电介质氧化物的至少一个多晶生长条件被改变，这导致电介质氧化物在所述层的厚度内的多晶性质的变化。

    METHOD FOR MANUFACTURING INSULATED-GATE MOS TRANSISTORS
    10.
    发明申请
    METHOD FOR MANUFACTURING INSULATED-GATE MOS TRANSISTORS 有权
    制造绝缘栅MOS晶体管的方法

    公开(公告)号：US20130099329A1

    公开(公告)日：2013-04-25

    申请号：US13659771

    申请日：2012-10-24

    Applicant: STMICROELECTRONICS (CROLLES 2) SAS

    Inventor： Mickael Gros-Jean ,  Clement Gaumer ,  Emmanuel Bayard Perrin

    IPC: H01L29/78 ,  H01L21/28

    CPC classification number: H01L21/76232 ,  H01L21/28229 ,  H01L21/823481 ,  H01L29/513 ,  H01L29/518

    Abstract: A method for defining an insulator in a semiconductor substrate includes forming a trench in the substrate, forming in the trench an insulating material having its upper surface arranged above the surface of the substrate, and forming a diffusion barrier layer in a portion of the insulating material located above the surface of the semiconductor substrate. Such insulators can be used, for example, to insulate and delineate electronic components or portions of components formed in the substrate.

    Abstract translation: 一种用于在半导体衬底中限定绝缘体的方法包括在衬底中形成沟槽，在沟槽中形成其上表面布置在衬底表面上方的绝缘材料，并在绝缘材料的一部分中形成扩散阻挡层 位于半导体衬底的表面上方。 这样的绝缘体可以用于例如绝缘并描绘形成在基板中的电子部件或部件。

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