公开(公告)号：US20170301378A1

公开(公告)日：2017-10-19

申请号：US15363270

申请日：2016-11-29

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics S.r.l.

Inventor： Francesco La Rosa ,  Gineuve Alieri

IPC: G11C7/06 ,  G11C8/10 ,  G11C5/14

CPC classification number: G11C7/065 ,  G11C5/14 ,  G11C7/08 ,  G11C8/10

Abstract: A read-amplifier circuit includes a core with a first input and a second input that are intended to receive in a measurement phase a differential signal arising from a first bit line and from a second bit line of the memory device. The circuit also includes a memory element with two inverters coupled in a crossed manner. The first and second inputs are respectively connected to two of the power supply nodes of the inverters via two transfer capacitors. A first controllable circuit is configured to temporarily render the memory element floating during an initial phase preceding the measurement phase and during the measurement phase.

公开(公告)号：US09792962B1

公开(公告)日：2017-10-17

申请号：US15363270

申请日：2016-11-29

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics S.r.l.

Inventor： Francesco La Rosa ,  Gineuve Alieri

IPC: G11C7/00 ,  G11C7/06 ,  G11C5/14 ,  G11C8/10

CPC classification number: G11C7/065 ,  G11C5/14 ,  G11C7/08 ,  G11C8/10

Abstract: A read-amplifier circuit includes a core with a first input and a second input that are intended to receive in a measurement phase a differential signal arising from a first bit line and from a second bit line of the memory device. The circuit also includes a memory element with two inverters coupled in a crossed manner. The first and second inputs are respectively connected to two of the power supply nodes of the inverters via two transfer capacitors. A first controllable circuit is configured to temporarily render the memory element floating during an initial phase preceding the measurement phase and during the measurement phase.

公开(公告)号：US09997213B2

公开(公告)日：2018-06-12

申请号：US15657408

申请日：2017-07-24

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Gineuve Alieri

IPC: G11C7/00 ,  G11C7/06 ,  G11C8/10 ,  G11C5/14

CPC classification number: G11C7/065 ,  G11C5/14 ,  G11C7/08 ,  G11C8/10

Abstract: A read-amplifier circuit includes a core with a first input and a second input that are intended to receive in a measurement phase a differential signal arising from a first bit line and from a second bit line of the memory device. The circuit also includes a memory element with two inverters coupled in a crossed manner. The first and second inputs are respectively connected to two of the power supply nodes of the inverters via two transfer capacitors. A first controllable circuit is configured to temporarily render the memory element floating during an initial phase preceding the measurement phase and during the measurement phase.

公开(公告)号：US20170323670A1

公开(公告)日：2017-11-09

申请号：US15657408

申请日：2017-07-24

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Gineuve Alieri

IPC: G11C7/06 ,  G11C8/10 ,  G11C5/14

CPC classification number: G11C7/065 ,  G11C5/14 ,  G11C7/08 ,  G11C8/10

Abstract: A read-amplifier circuit includes a core with a first input and a second input that are intended to receive in a measurement phase a differential signal arising from a first bit line and from a second bit line of the memory device. The circuit also includes a memory element with two inverters coupled in a crossed manner. The first and second inputs are respectively connected to two of the power supply nodes of the inverters via two transfer capacitors. A first controllable circuit is configured to temporarily render the memory element floating during an initial phase preceding the measurement phase and during the measurement phase.

公开(公告)号：US09984770B2

公开(公告)日：2018-05-29

申请号：US15140997

申请日：2016-04-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Gineuve Alieri

IPC: G11C29/00 ,  G11C29/52 ,  G06F11/10 ,  H03M13/29 ,  G11C29/04

CPC classification number: G11C29/52 ,  G06F11/1048 ,  G06F11/1068 ,  G11C29/4401 ,  G11C29/70 ,  G11C29/72 ,  G11C29/76 ,  G11C29/82 ,  G11C2029/0409 ,  H03M13/2906

Abstract: A method can be used for managing the operation of a non-volatile memory equipped with a system for correction of a single error and for detection of a double error. In the case of the detection of a defective bit line of the memory plane, a redundant bit line is assigned and the values of the bits of the memory cells of the defective line are copied into the memory cells of the redundant line and are inverted in the case of the detection of double errors by the system, or corrected by the system in the presence of single errors.

公开(公告)号：US09875798B2

公开(公告)日：2018-01-23

申请号：US15140856

申请日：2016-04-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Gineuve Alieri

IPC: G11C14/00 ,  G11C16/16 ,  G11C29/00 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C14/0018 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C29/76 ,  G11C29/785 ,  G11C29/789 ,  G11C29/82 ,  G11C29/84 ,  G11C29/846

Abstract: A non-volatile memory is erasable by page and equipped with a row redundancy mechanism. In the case of the detection of a defective row of the memory plane, the storing of the address of the row in a non-volatile register is carried out and a redundant row having a new address is assigned. In the case of an attempt to write to the defective row, a write to the redundant row is carried out. When writing to the redundant row, the new content of the redundant row is loaded into a volatile memory and, following an operation for writing to any other row of the memory plane, a re-loading of the new content of the redundant row into the volatile memory.

公开(公告)号：US20170163291A1

公开(公告)日：2017-06-08

申请号：US15140997

申请日：2016-04-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Gineuve Alieri

IPC: H03M13/29 ,  G11C29/52 ,  G06F11/10

CPC classification number: G11C29/52 ,  G06F11/1048 ,  G06F11/1068 ,  G11C29/4401 ,  G11C29/70 ,  G11C29/72 ,  G11C29/76 ,  G11C29/82 ,  G11C2029/0409 ,  H03M13/2906

Abstract: A method can be used for managing the operation of a non-volatile memory equipped with a system for correction of a single error and for detection of a double error. In the case of the detection of a defective bit line of the memory plane, a redundant bit line is assigned and the values of the bits of the memory cells of the defective line are copied into the memory cells of the redundant line and are inverted in the case of the detection of double errors by the system, or corrected by the system in the presence of single errors.

公开(公告)号：US10083753B2

公开(公告)日：2018-09-25

申请号：US15842476

申请日：2017-12-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Gineuve Alieri

IPC: G11C14/00 ,  G11C29/00 ,  G11C16/26 ,  G11C16/10 ,  G11C16/16

CPC classification number: G11C14/0018 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C29/76 ,  G11C29/785 ,  G11C29/789 ,  G11C29/82 ,  G11C29/84 ,  G11C29/846

Abstract: A non-volatile memory is erasable by page and equipped with a row redundancy mechanism. In the case of the detection of a defective row of the memory plane, the storing of the address of the row in a non-volatile register is carried out and a redundant row having a new address is assigned. In the case of an attempt to write to the defective row, a write to the redundant row is carried out. When writing to the redundant row, the new content of the redundant row is loaded into a volatile memory and, following an operation for writing to any other row of the memory plane, a re-loading of the new content of the redundant row into the volatile memory.

公开(公告)号：US20180108413A1

公开(公告)日：2018-04-19

申请号：US15842476

申请日：2017-12-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Gineuve Alieri

IPC: G11C14/00 ,  G11C29/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/16

CPC classification number: G11C14/0018 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C29/76 ,  G11C29/785 ,  G11C29/789 ,  G11C29/82 ,  G11C29/84 ,  G11C29/846

Abstract: A non-volatile memory is erasable by page and equipped with a row redundancy mechanism. In the case of the detection of a defective row of the memory plane, the storing of the address of the row in a non-volatile register is carried out and a redundant row having a new address is assigned. In the case of an attempt to write to the defective row, a write to the redundant row is carried out. When writing to the redundant row, the new content of the redundant row is loaded into a volatile memory and, following an operation for writing to any other row of the memory plane, a re-loading of the new content of the redundant row into the volatile memory.

公开(公告)号：US20170162264A1

公开(公告)日：2017-06-08

申请号：US15140856

申请日：2016-04-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Gineuve Alieri

IPC: G11C14/00 ,  G11C16/26 ,  G11C16/10 ,  G11C16/16 ,  G11C29/00

CPC classification number: G11C14/0018 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C29/76 ,  G11C29/785 ,  G11C29/789 ,  G11C29/82 ,  G11C29/84 ,  G11C29/846

Abstract: A non-volatile memory is erasable by page and equipped with a row redundancy mechanism. In the case of the detection of a defective row of the memory plane, the storing of the address of the row in a non-volatile register is carried out and a redundant row having a new address is assigned. In the case of an attempt to write to the defective row, a write to the redundant row is carried out. When writing to the redundant row, the new content of the redundant row is loaded into a volatile memory and, following an operation for writing to any other row of the memory plane, a re-loading of the new content of the redundant row into the volatile memory.