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公开(公告)号：US10127966B2
公开(公告)日：2018-11-13
申请号：US15389751
申请日：2016-12-23
Applicant: STMicroelectronics S.r.l. , STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Rousset) SAS
Inventor： Antonino Conte , Enrico Castaldo , Raul Andres Bianchi , Francesco La Rosa
Abstract: A reading circuit for a charge-retention circuit stage is provided with a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The reading circuit further has an operational amplifier having a first input terminal that is coupled to the floating node and receives a reading voltage, a second input terminal receives a reference voltage, and an output terminal on which it supplies an output voltage, the value of which is a function of the comparison between the reading voltage and the reference voltage and indicative of a residual charge in the storage capacitor. A shifting stage shifts the value of the reading voltage of the floating node, before the comparison is made between the reading voltage and the reference voltage for supplying the output voltage.
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公开(公告)号：US09698765B1
公开(公告)日：2017-07-04
申请号：US15049944
申请日：2016-02-22
Inventor： Francesco La Rosa , Antonino Conte
Abstract: A device includes a first and second inverters each having a signal input, signal output, high voltage supply terminal, and low voltage supply terminal. The signal input of the first inverter is coupled to the signal output of the second inverter, and the signal input of the second inverter is coupled to the signal output of the first inverter. A first transistor has a first conduction terminal coupled to a power supply node, a second conduction terminal coupled to the high voltage supply terminal of the first inverter, and a control terminal coupled to a first node. A second transistor has a first conduction terminal coupled to the power supply node, a second conduction terminal coupled to the high voltage supply terminal of the second inverter, and a control terminal coupled to a second node. First and second bit lines are capacitively coupled to the first and second nodes.
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公开(公告)号：US09627011B1
公开(公告)日：2017-04-18
申请号：US15212211
申请日：2016-07-16
Applicant: STMicroelectronics S.r.l , STMicroelectronics (Rousset) SAS
Inventor： Antonino Conte , Francesco La Rosa
CPC classification number: G11C7/08 , G11C7/062 , G11C7/12 , G11C16/28 , H03F3/45475 , H03F3/45968 , H03F2203/45212
Abstract: A method for operating a non-volatile memory device uses a sense amplifier that includes a first branch and a second branch. During a pre-charging step, a bit line of a memory array of the non-volatile memory device is biased in order to pre-charge the bit line. During the pre-charging step, an offset between the first branch and the second branch is detected and stored. During a reading step subsequent to the pre-charging step, a cell current is received from the bit line at the first branch and a reference current is received from a current-reference structure at the second branch. During the reading step, and amplified voltage is generated as a function of the cell current and the reference current. During the reading step, an output voltage is generated based on the amplified voltage compensated by the offset stored during the pre-charging step.
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公开(公告)号：US12057180B2
公开(公告)日：2024-08-06
申请号：US17934102
申请日：2022-09-21
Inventor： Francesco La Rosa , Antonino Conte , Francois Maugain
CPC classification number: G11C16/3445 , G11C16/14 , G11C16/26 , G11C16/3459 , G11C16/349 , H10B41/30 , H10B41/40
Abstract: In an embodiment a non-volatile memory device includes a memory array having a plurality of memory cells, a control unit operatively coupled to the memory array, a biasing stage controllable by the control unit and configured to apply a biasing configuration to the memory cells to perform a memory operation and a reading stage coupled to the memory array and controllable by the control unit, the reading stage configured to verify whether the memory operation has been successful based on a verify level, wherein the control unit is configured to adaptively modify a value of the verify level based on an ageing of the memory cells.
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公开(公告)号：US10281512B2
公开(公告)日：2019-05-07
申请号：US15387370
申请日：2016-12-21
Applicant: STMicroelectronics S.r.l. , STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Rousset) SAS
Inventor： Antonino Conte , Enrico Castaldo , Raul Andres Bianchi , Francesco La Rosa
Abstract: A method can be used for testing a charge-retention circuit for measurement of a time interval having a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The discharge element is configured to implement discharge of a charge stored in the storage capacitor by leakage through a corresponding dielectric. The method includes biasing the floating node at a reading voltage, detecting a biasing value of the reading voltage, implementing an operation of integration of the discharge current in the discharge element with the reading voltage kept constant at the biasing value, and determining an effective resistance value of the discharge element as a function of the operation of integration.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20180151231A1
公开(公告)日：2018-05-31
申请号：US15607636
申请日：2017-05-29
Inventor： Francesca Grande , Francesco La Rosa , Gianbattista Lo Giudice , Giovanni Matranga
CPC classification number: G11C16/16 , G11C16/26 , G11C16/3445
Abstract: A method can be used for reducing a memory operation time in a non-volatile memory device having a memory array with a number of memory cells. The method includes performing a first execution of the memory operation on a set of memory cells by applying a first biasing configuration, storing information associated to the first biasing configuration, and performing a second execution, subsequent to the first execution, of the memory operation on the same set of memory cells by applying a second biasing configuration that is determined according to the stored information associated to the first biasing configuration.
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公开(公告)号：US20170301378A1
公开(公告)日：2017-10-19
申请号：US15363270
申请日：2016-11-29
Inventor： Francesco La Rosa , Gineuve Alieri
Abstract: A read-amplifier circuit includes a core with a first input and a second input that are intended to receive in a measurement phase a differential signal arising from a first bit line and from a second bit line of the memory device. The circuit also includes a memory element with two inverters coupled in a crossed manner. The first and second inputs are respectively connected to two of the power supply nodes of the inverters via two transfer capacitors. A first controllable circuit is configured to temporarily render the memory element floating during an initial phase preceding the measurement phase and during the measurement phase.
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公开(公告)号：US09792962B1
公开(公告)日：2017-10-17
申请号：US15363270
申请日：2016-11-29
Inventor： Francesco La Rosa , Gineuve Alieri
Abstract: A read-amplifier circuit includes a core with a first input and a second input that are intended to receive in a measurement phase a differential signal arising from a first bit line and from a second bit line of the memory device. The circuit also includes a memory element with two inverters coupled in a crossed manner. The first and second inputs are respectively connected to two of the power supply nodes of the inverters via two transfer capacitors. A first controllable circuit is configured to temporarily render the memory element floating during an initial phase preceding the measurement phase and during the measurement phase.
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公开(公告)号：US12198756B2
公开(公告)日：2025-01-14
申请号：US18158232
申请日：2023-01-23
Inventor： Antonino Conte , Francesco La Rosa
Abstract: Unclonable function circuitry includes a plurality of pairs of phase-change memory cells in a virgin state, and sensing circuitry coupled to the plurality of pairs of phase-change memory cells in the virgin state. The sensing circuitry identifies a subset of the plurality of pairs of phase-change memory cells in the virgin state based on a reliability mask. Signs of differences of effective resistance values of the identified subset of the plurality of pairs of phase-change memory cells in the virgin state are sensed by the sensing circuitry. The sensing circuitry generates a string of bits based on the sensed signs of differences in the effective resistance values of the identified subset of the plurality of pairs of phase-change memory cells in the virgin state. Processing circuitry coupled to the unclonable function circuitry, in operation, executes one or more operations using the generated string of bits.
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公开(公告)号：US11615857B2
公开(公告)日：2023-03-28
申请号：US17224024
申请日：2021-04-06
Inventor： Francesco La Rosa , Enrico Castaldo , Francesca Grande , Santi Nunzio Antonino Pagano , Giuseppe Nastasi , Franco Italiano
Abstract: A semiconductor well of a non-volatile memory houses memory cells. The memory cells each have a floating gate and a control gate. Erasing of the memory cells includes biasing the semiconductor well with a first erase voltage having an absolute value greater than a breakdown voltage level of bipolar junctions of a control gate switching circuit of the memory. An absolute value of the first erase voltage is based on a comparison of a value of an indication of wear of the memory cells to a wear threshold value.
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