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    METHOD AND DEVICE FOR ON-DIE IMPEDANCE CALIBRATION
    2.
    发明申请
    METHOD AND DEVICE FOR ON-DIE IMPEDANCE CALIBRATION 有权

    公开(公告)号：US20240402278A1

    公开(公告)日：2024-12-05

    申请号：US18677437

    申请日：2024-05-29

    Applicant: STMicroelectronics International N.V.

    Inventor： Ravinder Kumar KUMAR ,  Saiyid Mohammad Irshad RIZVI

    IPC: G01R35/00 ,  G01R19/10 ,  G01R27/02

    Abstract: A test circuit is configured to test and calibrate an impedance of a driver of an integrated circuit. Testing the impedance includes driving first and second currents through the driver via a first contact pad and a ground metallization of the integrated circuit. Testing the impedance includes measuring the voltage at a test metalization while driving the first and second current while the test metalization is successively coupled to the first contact pad and the ground metallization while driving the first and second test currents.

    VOLTAGE COMPENSATION OF DIFFERENTIAL VOLTAGE SWING
    3.
    发明公开
    VOLTAGE COMPENSATION OF DIFFERENTIAL VOLTAGE SWING 审中-公开

    公开(公告)号：US20240291488A1

    公开(公告)日：2024-08-29

    申请号：US18582446

    申请日：2024-02-20

    Applicant: STMicroelectronics International N.V.

    Inventor： Ravinder KUMAR ,  Saiyid Mohammad Irshad RIZVI

    IPC: H03K19/003 ,  H03K19/0175

    CPC classification number: H03K19/00369 ,  H03K19/017545 ,  H03K19/017581

    Abstract: The present disclosure is directed to a voltage driver, where a combination of first and second resistance blocks controls a differential voltage swing on the outputs of the voltage driver. Variations of an input voltage are compensated by adding different values of the first resistance block to the second resistance block, while keeping a summation of the first and second resistance blocks at a constant value. Three different circuit diagrams are disclosed to generate these different resistances. In each circuit diagram, one or more control signals change the resistance of the combination of first and second resistance blocks. In some embodiments, the value of the second resistance block is changed by the first resistance block to maintain an impedance matching between a transmitter and a receiver, while changing of the first resistance block compensates for the differential voltage swing.

    HIGH PERFORMANCE I2C TRANSMITTER AND BUS SUPPLY INDEPENDENT RECEIVER, SUPPORTING LARGE SUPPLY VOLTAGE VARIATIONS
    4.
    发明申请
    HIGH PERFORMANCE I2C TRANSMITTER AND BUS SUPPLY INDEPENDENT RECEIVER, SUPPORTING LARGE SUPPLY VOLTAGE VARIATIONS 审中-公开

    公开(公告)号：US20190158085A1

    公开(公告)日：2019-05-23

    申请号：US15821387

    申请日：2017-11-22

    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

    Inventor： Saiyid Mohammad Irshad RIZVI ,  Atul DWIVEDI

    IPC: H03K17/687 ,  G05F3/24 ,  H03K19/0175 ,  G06F13/42

    Abstract: One or more embodiments are directed to inter-integrated circuit (I2C) transmitters, receivers, and devices that utilize a stable reference voltage for driving a pre-driver of the transmitter and for driving a first input stage of the receiver. One embodiment is directed to a device A device that includes an inter-integrated circuit (I2C) transmitter and an I2C receiver. The I2C transmitter includes a driver coupled to an I2C data line, and a pre-driver coupled to a variable first supply voltage, a second supply voltage, and a reference voltage. The pre-driver is configured to output a control signal to a control terminal of the driver. The I2C receiver includes a first stage coupled to the I2C data line, the variable first supply voltage, the second supply voltage, and the reference voltage.

    CMOS SCHMITT TRIGGER CIRCUIT AND ASSOCIATED METHODS
    5.
    发明申请
    CMOS SCHMITT TRIGGER CIRCUIT AND ASSOCIATED METHODS 有权
    CMOS SCHMITT触发器电路及相关方法

    公开(公告)号：US20160182022A1

    公开(公告)日：2016-06-23

    申请号：US14573129

    申请日：2014-12-17

    Applicant: STMicroelectronics International N.V.

    Inventor： Vinod KUMAR ,  Saiyid Mohammad Irshad RIZVI

    IPC: H03K3/3565

    CPC classification number: H03K3/3565

    Abstract: The Schmitt trigger circuit includes a signal input, a first inverter coupled to the signal input and configured to operate at a first voltage, and a second inverter coupled downstream of the first inverter and configured to operate at a second voltage lower than the first voltage. A protection device is coupled between the first inverter and the second inverter, and configured to limit a voltage input to the second inverter at the second voltage. A feedback circuit is coupled downstream of the protection device between the first inverter and the second inverter and configured to introduce hysteresis. An output circuit is coupled to the second inverter and configured to provide an output signal at the second voltage. The approach provides an architecture for 3.3V receivers designed by using 1.8V devices, without active power consumption from the I/O PAD during transition, and/or that supports CMOS standard levels for 1.8V and 3.3V receivers.

    Abstract translation: 施密特触发电路包括信号输入端，耦合到信号输入并被配置为以第一电压工作的第一反相器，以及耦合在第一反相器下游的第二反相器，并被配置为在低于第一电压的第二电压下工作。 保护装置耦合在第一反相器和第二反相器之间，并且被配置为将第二反相器的电压输入限制在第二电压。 反馈电路被耦合在第一逆变器和第二逆变器之间的保护装置的下游，并被配置为引入滞后。 输出电路耦合到第二反相器并且被配置为提供处于第二电压的输出信号。 该方法为通过使用1.8V器件设计的3.3V接收器提供了架构，在转换期间没有来自I / O PAD的有功功耗，和/或支持1.8V和3.3V接收器的CMOS标准电平。

    HIGH-VOLTAGE FAULT PROTECTION CIRCUIT
    8.
    发明公开
    HIGH-VOLTAGE FAULT PROTECTION CIRCUIT 审中-公开

    公开(公告)号：US20240039537A1

    公开(公告)日：2024-02-01

    申请号：US18356146

    申请日：2023-07-20

    Applicant: STMicroelectronics International N.V.

    Inventor： Manoj KUMAR ,  Paras GARG ,  Saiyid Mohammad Irshad RIZVI

    IPC: H03K19/003 ,  H03K19/0185

    CPC classification number: H03K19/00315 ,  H03K19/018521

    Abstract: The present disclosure is directed to a high-voltage fault protection for an interface circuit. The interface circuit is transmitting data signals through an output driver to an external circuit coupled to a PAD contact. The output driver includes pull-up and pull-down drivers. The pull-up driver includes two series PMOS coupled between a voltage supply and the PAD. The pull-down driver includes two series NMOS coupled between the PAD and a ground node. A first safe signal is coupled to one PMOS. A first circuit scheme is designed to generate the first safe signal to be low-logical level voltage when the PAD voltage is lower than a threshold, while being high-logical level voltage when the PAD voltage is higher than the threshold. A second circuit scheme is designed to control one of the series NMOS to be in OFF state when the PAD voltage is higher than the threshold.

    GLITCH FILTER HAVING A SWITCHED CAPACITANCE AND RESET STAGES
    9.
    发明申请
    GLITCH FILTER HAVING A SWITCHED CAPACITANCE AND RESET STAGES 有权

    公开(公告)号：US20210336606A1

    公开(公告)日：2021-10-28

    申请号：US17223963

    申请日：2021-04-06

    Applicant: STMicroelectronics International N.V.

    Inventor： Manoj Kumar TIWARI ,  Saiyid Mohammad Irshad RIZVI

    IPC: H03H11/04 ,  G06F1/10

    Abstract: A glitch filter is provided. The glitch filter receives an input signal and sets a voltage level of an intermediary input node in accordance with a state of the input signal. The glitch filter charges or discharges a switched capacitance based on the voltage level of the intermediary input node and charges or discharges a filter capacitance based on a charge of the switched capacitance. The glitch filter sets a state of an output signal based on the charge of the filter capacitance. The glitch filter includes a reset stage that at least partially filters a burst of glitches in the input signal from the output signal by controlling the charge of the switched capacitance based on the state of the input signal and the state of the output signal.

    BIASING CASCODE TRANSISTORS OF AN OUTPUT BUFFER CIRCUIT FOR OPERATION OVER A WIDE RANGE OF SUPPLY VOLTAGES
    10.
    发明申请
    BIASING CASCODE TRANSISTORS OF AN OUTPUT BUFFER CIRCUIT FOR OPERATION OVER A WIDE RANGE OF SUPPLY VOLTAGES 审中-公开

    公开(公告)号：US20190312575A1

    公开(公告)日：2019-10-10

    申请号：US16253410

    申请日：2019-01-22

    Applicant: STMicroelectronics International N.V.

    Inventor： Manoj Kumar Kumar TIWARI ,  Saiyid Mohammad Irshad RIZVI

    IPC: H03K17/082 ,  H03K17/687 ,  G05F3/16 ,  H03K19/0185

    Abstract: An output stage of an output buffer circuit includes a first drive transistor and a first cascode transistor (coupled in series between a first supply node and an output node) and a second drive transistor and a second cascode transistor (coupled in series between the output node and a second supply node). Gates of the first and second cascode transistors are biased with first and second bias voltages, respectively. The first bias voltage equals the first supply voltage at the first supply node when the first supply voltage is less than a threshold, and is fixed at a fixed voltage for any first supply voltage exceeding the threshold voltage. The second bias voltage equals a fixed voltage when the first supply voltage is less than a threshold voltage, and is offset from the first supply voltage by a fixed difference for any first supply voltage exceeding the threshold.

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