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    System and method for improving memory performance and identifying weak bits
    1.
    发明授权
    System and method for improving memory performance and identifying weak bits 有权
    用于提高记忆性能和识别弱位的系统和方法

    公开(公告)号：US09543044B2

    公开(公告)日：2017-01-10

    申请号：US14074341

    申请日：2013-11-07

    Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.R.L.

    Inventor： Abhishek Jain ,  Andrea Mario Veggetti ,  Amit Chhabra

    IPC: G11C29/48 ,  G06F1/08 ,  G11C29/24 ,  G11C29/52 ,  G11C29/54

    CPC classification number: G11C29/48 ,  G06F1/08 ,  G06F11/00 ,  G11C29/24 ,  G11C29/52

    Abstract: According to an embodiment described herein, a method for testing a memory includes receiving an address and a start signal at a memory, and generating a first detector pulse at a test circuit in response to the start signal. The first detector pulse has a leading edge and a trailing edge. A data transition of a bit associated with the address is detected. The bit is a functional bit. The method further includes determining whether the bit is a weak bit by determining whether the data transition occurred after the trailing edge.

    Abstract translation: 根据本文描述的实施例，用于测试存储器的方法包括在存储器处接收地址和起始信号，并且响应于起始信号在测试电路产生第一检测器脉冲。 第一检测器脉冲具有前沿和后沿。 检测与地址相关联的位的数据转换。 该位是一个功能位。 该方法还包括通过确定在后沿之后是否发生数据转换来确定该位是否为弱位。

    SOFT ERROR-RESILIENT LATCH
    2.
    发明申请
    SOFT ERROR-RESILIENT LATCH 审中-公开

    公开(公告)号：US20200007129A1

    公开(公告)日：2020-01-02

    申请号：US16452051

    申请日：2019-06-25

    Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

    Inventor： Andrea Mario Veggetti ,  Abhishek Jain

    IPC: H03K19/003 ,  H03K3/037 ,  H03K3/356 ,  G01R31/3181 ,  G11C7/10

    Abstract: A latch is provided. The latch includes a plurality of storage nodes including a plurality of data storage nodes configured to store a data bit having one of two states and a plurality of complementary data storage nodes configured to store a complement of the data bit. The latch includes a plurality of supply voltage multi-dependency stages respectively corresponding to the plurality of storage nodes. Each supply voltage multi-dependency stage has an output coupled to a storage node and at least two control inputs respectively coupled to at least two other storage nodes of the plurality of storage nodes. The supply voltage multi-dependency stage is configured to cause a state of the data bit stored in the storage node to change from a first state to a second state in response a change in both states of two data bits respectively stored in the at least two other storage nodes.

    System and Method for Improving Memory Performance and Identifying Weak Bits
    4.
    发明申请
    System and Method for Improving Memory Performance and Identifying Weak Bits 有权
    提高内存性能和识别弱位的系统和方法

    公开(公告)号：US20150127998A1

    公开(公告)日：2015-05-07

    申请号：US14074341

    申请日：2013-11-07

    Applicant: STMicroelectronics International N.V.

    Inventor： Andrea Mario Veggetti ,  Abhishek Jain ,  Amit Chhabra

    IPC: G11C29/48 ,  G11C7/22 ,  G06F1/08

    CPC classification number: G11C29/48 ,  G06F1/08 ,  G06F11/00 ,  G11C29/24 ,  G11C29/52

    Abstract: According to an embodiment described herein, a method for testing a memory includes receiving an address and a start signal at a memory, and generating a first detector pulse at a test circuit in response to the start signal. The first detector pulse has a leading edge and a trailing edge. A data transition of a bit associated with the address is detected. The bit is a functional bit. The method further includes determining whether the bit is a weak bit by determining whether the data transition occurred after the trailing edge.

    Abstract translation: 根据本文描述的实施例，用于测试存储器的方法包括在存储器处接收地址和起始信号，并且响应于起始信号在测试电路产生第一检测器脉冲。 第一检测器脉冲具有前沿和后沿。 检测与地址相关联的位的数据转换。 该位是一个功能位。 该方法还包括通过确定在后沿之后是否发生数据转换来确定该位是否为弱位。

    On chip test architecture for continuous time delta sigma analog-to-digital converter
    6.
    发明授权
    On chip test architecture for continuous time delta sigma analog-to-digital converter 有权

    公开(公告)号：US11901919B2

    公开(公告)日：2024-02-13

    申请号：US17723225

    申请日：2022-04-18

    Applicant: STMicroelectronics International N.V.

    Inventor： Ankur Bal ,  Abhishek Jain ,  Sharad Gupta

    IPC: H03M3/00

    CPC classification number: H03M3/378 ,  H03M3/46 ,  H03M3/496

    Abstract: An integrated circuit includes a continuous time delta sigma analog-to-digital converter (CTDS ADC) and a test circuit for testing the CTDS ADC. The test circuit converts multi-bit digital reference data to a single-bit digital stream. The test circuit then passes the single-bit digital stream to a finite impulse response digital-to-analog converter (FIR DAC). The FIR DAC converts the single-bit digital stream to an analog test signal. The analog test signal is then passed to the CTDS ADC. The CTDS ADC converts the analog test signal to digital test data. The test circuit analyzes the digital test data to determine the accuracy of the CTDS ADC.

    Real-Time Optimization of Many-Core Systems
    9.
    发明申请
    Real-Time Optimization of Many-Core Systems 审中-公开
    多核系统的实时优化

    公开(公告)号：US20160147545A1

    公开(公告)日：2016-05-26

    申请号：US14549332

    申请日：2014-11-20

    Applicant: STMicroelectronics International N.V.

    Inventor： Abhishek Jain ,  Chittoor Parthasarathy

    IPC: G06F9/445 ,  G06F11/34 ,  G06F11/30

    CPC classification number: G06F9/44505 ,  G06F11/008 ,  G06F11/3024 ,  G06F11/3051 ,  G06F11/3055 ,  G06F11/3433

    Abstract: An embodiment is a device including a processor having a plurality of cores, each of the plurality of cores including a real-time monitoring circuit, each of the real-time monitoring circuits configured to determine a status of the respective core and generate status signals based on the determined status in the respective core. The device further comprising a controller configured to: receive the status signals from real-time monitoring circuits of the plurality of cores; and configure an operation of each of the plurality of cores based on their respective status signals.

    Abstract translation: 实施例是包括具有多个核的处理器的装置，所述多个核心中的每一个包括实时监视电路，所述实时监视电路中的每一个被配置为确定各个核心的状态并基于 在各自核心的确定状态。 该装置还包括控制器，其被配置为：从多个核心的实时监控电路接收状态信号; 并且基于它们各自的状态信号来配置多个核心中的每一个的操作。

    System and Method for Critical Path Replication
    10.
    发明申请
    System and Method for Critical Path Replication 有权
    关键路径复制的系统和方法

    公开(公告)号：US20140167812A1

    公开(公告)日：2014-06-19

    申请号：US13715721

    申请日：2012-12-14

    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

    Inventor： Abhishek Jain ,  Chittoor Parthasarathy ,  Kallol Chatterjee

    IPC: H03K19/003 ,  G06F17/50

    CPC classification number: H03K19/003 ,  G06F17/5045 ,  G06F2217/12 ,  Y02P90/265

    Abstract: Disclosed is a system and method for providing a critical path replica system in a circuit. A critical path replica system is created by determining a critical path in a circuit, generating a critical path replica circuit, generating a circuit blueprint, and creating the blueprinted circuit. The circuit comprises a functional logic module having functional logic elements and replica logic modules having logic elements. Each logic element is configured to replicate one or more of the functional logic elements and process a test signal. A replica error detection module analyzes the processed signal to determine whether a timing violation has occurred. In some embodiments, the replica logic module further comprises one or more load modules. A replica controller may modify operation of the circuit based on reported errors. A replica mode select module sets the replica logic module to an aging test mode or a timing sensor mode.

    Abstract translation: 公开了一种用于在电路中提供关键路径复制系统的系统和方法。 通过确定电路中的关键路径，产生关键路径复制电路，生成电路蓝图以及创建蓝图电路来创建关键路径复制系统。 该电路包括具有功能逻辑元件的功能逻辑模块和具有逻辑元件的复制逻辑模块。 每个逻辑元件被配置为复制一个或多个功能逻辑元件并处理测试信号。 复制错误检测模块分析处理的信号以确定是否发生定时冲突。 在一些实施例中，副本逻辑模块还包括一个或多个加载模块。 复制控制器可以基于报告的错误来修改电路的操作。 复制模式选择模块将副本逻辑模块设置为老化测试模式或定时传感器模式。

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