公开(公告)号：US20040228163A1

公开(公告)日：2004-11-18

申请号：US10782737

申请日：2004-02-18

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Osama Khouri ,  Claudio Resta

IPC: G11C011/00

CPC classification number: G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2213/79

Abstract: A phase change memory has an array formed by a plurality of cells, each including a memory element of calcogenic material and a selection element connected in series to the memory element; a plurality of address lines connected to the cells; a write stage and a reading stage connected to the array. The write stage is formed by current generators, which supply preset currents to the selected cells so as to modify the resistance of the memory element. Reading takes place in voltage, by appropriately biasing the selected cell and comparing the current flowing therein with a reference value.

Abstract translation: 相变存储器具有由多个单元形成的阵列，每个单元包括煅烧材料的存储元件和与存储元件串联连接的选择元件; 连接到所述单元的多个地址线; 连接到阵列的写阶段和阅读阶段。 写入级由电流发生器形成，电流发生器向所选择的单元提供预设电流，以便改变存储元件的电阻。 读取通过适当地偏置所选择的单元并将其中流动的电流与参考值进行比较来进行电压。

公开(公告)号：US20030223285A1

公开(公告)日：2003-12-04

申请号：US10331185

申请日：2002-12-27

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Osama Khouri ,  Ferdinando Bedeschi

IPC: G11C029/00

CPC classification number: G11C13/0026 ,  G11C7/22 ,  G11C13/0038 ,  G11C16/24 ,  G11C2216/22

Abstract: A nonvolatile memory device is described comprising a memory array, a row decoder and a column selector for addressing the memory cells of the memory array, and a biasing stage for biasing the array access device terminal of the addressed memory cell. The biasing stage is arranged between the column selector and the memory array and comprises a biasing transistor having a drain terminal connected to the column selector, a source terminal connected to the array access device terminal of the addressed memory cell, and a gate terminal receiving a logic driving signal, the logic levels of which are defined by precise and stable voltages and are generated by a logic block and an output buffer cascaded together. The output buffer may be supplied with either a read voltage or a program voltage supplied by a multiplexer. The biasing transistor may be either included as part of the column selector and formed by the selection transistor which is closest to the addressed memory cell or distinct from the selection transistors of the column selector.

Abstract translation: 描述了一种非易失性存储器件，其包括用于寻址存储器阵列的存储单元的存储器阵列，行解码器和列选择器，以及用于偏置寻址的存储器单元的阵列存取器件端子的偏置级。 偏置级布置在列选择器和存储器阵列之间，并且包括偏置晶体管，漏极端子连接到列选择器，源极端子连接到寻址存储单元的阵列存取器件端子，栅极端子接收 逻辑驱动信号，其逻辑电平由精确和稳定的电压定义，并由逻辑块和输出缓冲器一起级联产生。 可以向输出缓冲器提供由多路复用器提供的读取电压或编程电压。 偏置晶体管可以被包括为列选择器的一部分，并且由选择晶体管形成，该选择晶体管最靠近寻址的存储单元或与列选择器的选择晶体管不同。

公开(公告)号：US20040211953A1

公开(公告)日：2004-10-28

申请号：US10756195

申请日：2004-01-13

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Osama Khouri ,  Giorgio Pollaccia ,  Fabio Pellizzer

IPC: H01L047/00 ,  H01L021/336 ,  H01L021/4763

CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L45/122 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/16

Abstract: A contact structure for a PCM device is formed by an elongated formation having a longitudinal extension parallel to the upper surface of the body and an end face extending in a vertical plane. The end face is in contact with a bottom portion of an active region of chalcogenic material so that the dimensions of the contact area defined by the end face are determined by the thickness of the elongated formation and by the width thereof.

Abstract translation: 用于PCM装置的接触结构通过具有平行于主体的上表面的纵向延伸的细长结构和在垂直平面中延伸的端面形成。 端面与​​硫属活性材料的活性区域的底部接触，使得由端面限定的接触面积的尺寸由细长结构体的厚度及其宽度确定。

公开(公告)号：US20030185047A1

公开(公告)日：2003-10-02

申请号：US10319439

申请日：2002-12-12

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Osama Khouri ,  Ferdinando Bedeschi ,  Giorgio Bosisio ,  Fabio Pellizzer

IPC: G11C011/00

CPC classification number: G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

Abstract: The phase-change nonvolatile memory array is formed by a plurality of memory cells extending in a first and in a second direction orthogonal to each other. A plurality of column-selection lines extend parallel to the first direction. A plurality of word-selection lines extend parallel to the second direction. Each memory cell includes a PCM storage element and a selection transistor. A first terminal of the selection transistor is connected to a first terminal of the PCM storage element, and the control terminal of the selection transistor is connected to a respective word-selection line. A second terminal of the PCM storage element is connected to a respective column-selection line, and a second terminal of the selection transistor is connected to a reference-potential region while reading and programming the memory cells.

Abstract translation: 相变非易失性存储器阵列由在彼此正交的第一和第二方向上延伸的多个存储单元形成。 多个列选择线平行于第一方向延伸。 多个字选择线平行于第二方向延伸。 每个存储单元包括PCM存储元件和选择晶体管。 选择晶体管的第一端子连接到PCM存储元件的第一端子，并且选择晶体管的控制端子连接到相应的字选择线。 PCM存储元件的第二端子连接到相应的列选择线，并且在读取和编程存储器单元的同时，选择晶体管的第二端子连接到参考电位区域。

公开(公告)号：US20030107428A1

公开(公告)日：2003-06-12

申请号：US10290030

申请日：2002-11-07

Applicant: STMicroelectronics S.r.l.

Inventor： Osama Khouri ,  Andrea Pierin ,  Dario Soltesz ,  Guido Torelli

IPC: G05F003/02

CPC classification number: G11C5/145 ,  H02M3/073 ,  H02M2001/0032 ,  H02M2003/075 ,  H02M2003/077 ,  Y02B70/16

Abstract: A charge pump circuit, connected between a first voltage reference and an output terminal, comprises at least two stages comprising an elementary charge pump circuit connected between said first voltage reference and said output terminal, and adjustment circuitry connected between said output terminal and respective control terminals of said at least two stages. This circuitry is arranged to select for actuation an appropriate combination of these elementary stages according to the current absorbed from a load connected to the output terminal.

Abstract translation: 连接在第一参考电压和输出端子之间的电荷泵电路包括至少两个级，包括连接在所述第一参考电压和所述输出端子之间的基本电荷泵电路，以及连接在所述输出端子和相应控制端子之间的调节电路 的至少两个阶段。 该电路被设置为根据从连接到输出端子的负载吸收的电流来选择这些基本级的适当组合。

公开(公告)号：US20040151023A1

公开(公告)日：2004-08-05

申请号：US10715883

申请日：2003-11-18

Applicant: STMicroelectronics S.r.I. ,  OVONYX Inc.

Inventor： Osama Khouri ,  Ferdinando Bedeschi ,  Claudio Resta

IPC: G11C011/00

CPC classification number: G11C7/04 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2029/5002 ,  G11C2213/79

Abstract: A phase change memory includes a temperature sensor having a resistance variable with temperature with the same law as a phase-change storage element. The temperature sensor is formed by a resistor of chalcogenic material furnishing an electrical quantity that reproduces the relationship between the resistance of a phase change memory cell and temperature; the electrical quantity is processed so as to generate reference quantities as necessary for writing and reading the memory cells. The chalcogenic resistor has the same structure as a memory cell and is programmed with precision, preferably in the reset state.

Abstract translation: 相变存储器包括具有与相变存储元件相同定律的具有温度的电阻变化的温度传感器。 该温度传感器是由一个硫化物材料的电阻器形成的，它提供一个再现相变存储器单元电阻和温度之间的关系的电量; 对电量进行处理，以便产生写入和读取存储单元所需的参考量。 硫属电阻器具有与存储器单元相同的结构，并且精确地编程，优选地处于复位状态。

公开(公告)号：US20020097627A1

公开(公告)日：2002-07-25

申请号：US09960851

申请日：2001-09-21

Applicant: STMicroelectronics S.r.l.

Inventor： Andrea Sacco ,  Osama Khouri ,  Rino Micheloni ,  Guido Torelli

IPC: G11C005/00

CPC classification number: G11C16/08 ,  G11C5/147 ,  G11C8/08 ,  G11C8/10 ,  G11C8/14

Abstract: Described herein is a nonvolatile memory comprising a memory array organized according to global word lines and local word lines; a global row decoder; a local row decoder; a first supply stage for supplying the global row decoder; and a second supply stage for supplying the local row decoder; and a third supply stage for biasing the drain and source terminals of the memory cells of the memory array. Each of the supply stages comprises a respective resistive divider formed by a plurality of series-connected resistors, and a plurality of pass-gate CMOS switches each connected in parallel to a respective resistor. The nonvolatile memory further comprises a control circuit for controlling the pass-gate CMOS switches of the supply stages, and a switching circuit for selectively connecting the supply input of the control circuit to the output of the second supply stage during reading and programming of the memory, and to the output of the third supply stage during erasing of the memory.

Abstract translation: 这里描述的是一种非易失性存储器，包括根据全局字线和本地字线组织的存储器阵列; 全球排解码器; 一个本地行解码器; 用于提供全球行解码器的第一供应级; 以及用于提供本地行解码器的第二供应级; 以及用于偏置存储器阵列的存储单元的漏极和源极端子的第三供电级。 每个供电级包括由多个串联电阻器形成的相应电阻分压器，以及各自并联连接到相应电阻器的多个通栅CMOS开关。 非易失性存储器还包括用于控制供电级的通过栅极CMOS开关的控制电路和用于在存储器的读取和编程期间将控制电路的电源输入选择性地连接到第二电源级的输出的开关电路 并且在擦除存储器期间到达第三电源级的输出。

公开(公告)号：US20020196171A1

公开(公告)日：2002-12-26

申请号：US10060076

申请日：2002-01-29

Applicant: STMicroelectronics S.r.l.

Inventor： Rino Micheloni ,  Osama Khouri ,  Andrea Pierin ,  Stefano Gregori ,  Guido Torelli

IPC: H03M001/14

CPC classification number: G11C11/56 ,  G11C27/005 ,  H03M1/146 ,  H03M1/361

Abstract: An analog-to-digital conversion method and device for a multilevel non-volatile memory devicethat includes a multilevel memory cell. The method comprises a first step of converting the most significant bits contained in the memory cell, followed by a second step of converting the least significant bits. The first step is completed within a time interval corresponding to the rise transient of the gate voltage, and the second step is initiated at the end of the transient. Also disclosed is a scheme for error control coding in multilevel Flash memories. The n bits stored in a single memory cell are organized in different nullbit-layersnull, which are independent from one another. Error correction is carried out separately for each bit-layer. The correction of any failure in a single memory cell is achieved by using a simple error control code providing single-bit correction, regardless of the number of bits stored in a single cell.

Abstract translation: 用于多电平非易失性存储器设备的模数转换方法和装置包括多电平存储器单元。 该方法包括转换存储单元中包含的最高有效位的第一步骤，随后转换最低有效位的第二步骤。 在对应于栅极电压的上升瞬变的时间间隔内完成第一步，并且在瞬态结束时启动第二步。 还公开了一种用于多电平闪存中的错误控制编码的方案。 存储在单个存储器单元中的n位被组织在彼此独立的不同“位层”中。 针对每个位层分别执行错误校正。 通过使用提供单位校正的简单误差控制代码来实现单个存储器单元中的任何故障的校正，而不管存储在单个单元中的位数。

公开(公告)号：US20040170057A1

公开(公告)日：2004-09-02

申请号：US10748696

申请日：2003-12-30

Applicant: STMicroelectronics S.r.l.

Inventor： Osama Khouri ,  Roberto Ravasio ,  Rino Micheloni ,  Giovanni Campardo

IPC: G11C011/34

CPC classification number: G11C29/76

Abstract: The device includes a circuit for sector remapping having a CAM (Content Addressable Memory) unit, associated to and in data communication with a multiplexer unit. The CAM unit detects that a sector is defective, it provides the pre-programmed address of a replacing sector and it activates the multiplexer which performs the replacement. The defective sectors and the corresponding locations of the address map are therefore advantageously positioned to the rear to the addressing area. The addressing area is consequently continuous, thus allowing the information to be easily stored and retrieved.

Abstract translation: 该设备包括用于扇区重新映射的电路，其具有与多路复用器单元相关联并且与多路复用器单元进行数据通信的CAM（内容可寻址存储器）单元。 CAM单元检测到扇区有故障，它提供替换扇区的预编程地址，并激活执行替换的多路复用器。 因此，有缺陷的扇区和地址图的相应位置有利地位于寻址区的后方。 因此，寻址区域是连续的，从而可以容易地存储和检索信息。