公开(公告)号：US20150108468A1

公开(公告)日：2015-04-23

申请号：US14468601

申请日：2014-08-26

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jun Hyuk CHEON ,  Mu Gyeom KIM

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/417 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7869 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02675 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78606 ,  H01L2029/42388

Abstract: A thin film transistor may include a substrate, an oxide semiconductor layer on the substrate, a first insulating layer on the oxide semiconductor layer, a gate electrode on the first insulating layer, a second insulating layer on the gate electrode, and a source electrode and a drain electrode on the second insulating layer and facing each other. Each of the source electrode and the drain electrode may be connected with the oxide semiconductor layer through a contact hole in the second insulating layer. The oxide semiconductor layer may include a polycrystalline semiconductor.

Abstract translation: 薄膜晶体管可以包括衬底，衬底上的氧化物半导体层，氧化物半导体层上的第一绝缘层，第一绝缘层上的栅电极，栅电极上的第二绝缘层和源电极，以及 在第二绝缘层上的漏电极并且彼此面对。 源电极和漏电极中的每一个可以通过第二绝缘层中的接触孔与氧化物半导体层连接。 氧化物半导体层可以包括多晶半导体。

公开(公告)号：US20190148414A1

公开(公告)日：2019-05-16

申请号：US16243702

申请日：2019-01-09

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Hyun Jin CHO ,  Joon-Hwa BAE ,  Byoung Kwon CHOO ,  Byung Hoon KANG ,  Kwang Suk KIM ,  Woo Jin CHO ,  Jun Hyuk CHEON

IPC: H01L27/12 ,  B24B31/00 ,  H01L21/3105 ,  G09G3/3233 ,  C09G1/02

CPC classification number: H01L27/1248 ,  B24B31/00 ,  C09G1/02 ,  G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0847 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31053 ,  H01L22/26 ,  H01L27/1244 ,  H01L27/1255 ,  H01L27/1262 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3265 ,  H01L27/3276 ,  H01L29/78675 ,  H01L2227/323

Abstract: A method for manufacturing a display device includes forming a first gate metal wire on a substrate, forming a first insulation layer that covers the first gate metal wire, forming a second gate metal wire on the first insulation layer, forming a second main insulation layer that covers the second gate metal wire, forming a second auxiliary insulation layer on the second main insulation layer, forming an exposed portion of an upper surface of the second main insulation layer by polishing the second auxiliary insulation layer, and forming a first data metal wire on the second main insulation layer and the second auxiliary insulation layer.

公开(公告)号：US20180047762A1

公开(公告)日：2018-02-15

申请号：US15671638

申请日：2017-08-08

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Joon-Hwa BAE ,  Byoung Kwon CHOO ,  Byung Hoon KANG ,  Woo Jin CHO ,  Hyun Jin CHO ,  Jun Hyuk CHEON ,  Jee-Hyun LEE

IPC: H01L27/12 ,  H01L21/02 ,  H01L29/786

CPC classification number: H01L27/1285 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/02675 ,  H01L21/02697 ,  H01L21/30625 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76834 ,  H01L27/1222 ,  H01L27/127 ,  H01L29/66757 ,  H01L29/78672 ,  H01L29/7869 ,  H01L29/78696

Abstract: A method of manufacturing a transistor display panel and a transistor display panel, the method including forming a polycrystalline silicon layer on a substrate; forming an active layer by patterning the polycrystalline silicon layer; forming a first insulating layer covering the substrate and the active layer; exposing the active layer by polishing the first insulating layer using a polishing apparatus; and forming a second insulating layer that contacts the first insulating layer and the active layer, wherein exposing the active layer by polishing the first insulating layer includes coating a first slurry on a surface of the first insulating layer, the first slurry reducing a polishing rate of the active layer.

公开(公告)号：US20180114819A1

公开(公告)日：2018-04-26

申请号：US15605431

申请日：2017-05-25

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Byung Hoon KANG ,  Kwang Suk KIM ,  Joon-Hwa BAE ,  Woo Jin CHO ,  Hyun Jin CHO ,  Jun Hyuk CHEON ,  Byoung Kwon CHOO

IPC: H01L27/32

CPC classification number: H01L27/3248 ,  H01L27/3276 ,  H01L2227/323

Abstract: A method of manufacturing a display device includes: forming an active layer on a substrate; forming a first insulation layer covering the active layer; forming a gate metal line on the first insulation layer; forming a third insulation layer covering the gate metal line and including a silicon oxide; forming a fourth insulation layer including a silicon nitride on the third insulation layer; forming a fifth insulation layer including a silicon oxide on the fourth insulation layer; arranging a blocking member over a region in which the active layer and the gate metal line overlap; forming a fifth auxiliary insulation layer by doping nitrogen ions in the fifth insulation layer; and exposing a part of an upper surface of the fourth insulation layer by removing a portion of a fifth main insulation layer of the fifth insulation layer which does not overlap the fifth auxiliary insulation layer.

公开(公告)号：US20180043501A1

公开(公告)日：2018-02-15

申请号：US15664166

申请日：2017-07-31

Applicant: Samsung Display Co., Ltd.

Inventor： Hyun Jin CHO ,  Joon-Hwa BAE ,  Byoung Kwon CHOO ,  Byung Hoon KANG ,  Jun Hyuk CHEON ,  Jeong-Hye CHOI ,  Young Ho JEONG ,  Woo Jin CHO

IPC: B24B37/34 ,  B24B53/017 ,  B24B37/10

CPC classification number: B24B37/345 ,  B24B37/10 ,  B24B53/017

Abstract: A substrate polishing system includes: a polishing machine and a substrate transporter. The polishing machine includes: a lower surface plate to which a substrate is mounted, and an upper surface plate which faces the lower surface plate and polishes the substrate in cooperation with the lower surface plate, the upper surface plate having a larger area than the substrate mounted on the lower surface plate. The substrate transporter is adjacent to the polishing machine and commonly transports the substrate to and from the polishing machine in a first direction, attaches the substrate to the lower surface plate before polishing thereof, and separates from the lower surface plate the substrate after polishing thereof.

公开(公告)号：US20150357395A1

公开(公告)日：2015-12-10

申请号：US14530506

申请日：2014-10-31

Applicant: Samsung Display Co., Ltd.

Inventor： Jun Hyuk CHEON ,  Kwang Jun KIM ,  Hee June KWAK ,  Mu Gyeom KIM

IPC: H01L27/32 ,  H01L51/52

CPC classification number: H01L27/3276 ,  H01L27/3213 ,  H01L27/3216 ,  H01L27/3218 ,  H01L27/3237 ,  H01L51/0097 ,  H01L51/52 ,  H01L2251/5338

Abstract: A flexible display device includes a folding section formed on a flexible substrate, a flat section connected to the folding section, and a display area for displaying an image, wherein the display area is formed on the folding section and the flat section, wherein each of the display areas of the folding section and the flat section includes a plurality of pixels and a plurality of wires for supplying electrical signals to the pixels, and wherein the wires in the display area of the folding section include a winding wire extending in a winding configuration on the flexible substrate.

Abstract translation: 柔性显示装置包括形成在柔性基板上的折叠部分，连接到折叠部分的平坦部分和用于显示图像的显示区域，其中显示区域形成在折叠部分和平坦部分上， 折叠部分和平坦部分的显示区域包括多个像素和用于向像素提供电信号的多条电线，并且其中折叠部分的显示区域中的电线包括以缠绕配置延伸的绕组线 在柔性基板上。

公开(公告)号：US20180358386A1

公开(公告)日：2018-12-13

申请号：US15971435

申请日：2018-05-04

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： BYOUNG KWON CHOO ,  Joon Hwa BAE ,  Hyun Jin CHO ,  Jun Hyuk CHEON ,  Zi Yeon YOON ,  Woo Jin CHO ,  Sung Hwan CHOI ,  Jeong Hye CHOI

IPC: H01L27/12 ,  G02F1/1362 ,  G02F1/1368 ,  H01L27/32 ,  H01L21/321

Abstract: A thin-film transistor (TFT) array substrate is provided. The TFT array substrate includes a base substrate, a semiconductor layer disposed on the base substrate, an insulating layer disposed on the semiconductor layer, and a gate electrode disposed on the insulating layer. A top surface of a portion of the insulating layer overlapping the semiconductor layer in a plan view of the base substrate and a top surface of the gate electrode are placed on the same level.

公开(公告)号：US20180108684A1

公开(公告)日：2018-04-19

申请号：US15702797

申请日：2017-09-13

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Hyun Jin CHO ,  Joon-Hwa BAE ,  Byoung Kwon CHOO ,  Byung Hoon KANG ,  Kwang Suk KIM ,  Woo Jin CHO ,  Jun Hyuk CHEON

IPC: H01L27/12 ,  H01L21/3105 ,  H01L21/66 ,  C09G1/02 ,  B24B31/00

CPC classification number: H01L27/1248 ,  B24B31/00 ,  C09G1/02 ,  G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0847 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31053 ,  H01L22/26 ,  H01L27/1244 ,  H01L27/1255 ,  H01L27/1262 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3265 ,  H01L27/3276 ,  H01L29/78675 ,  H01L2227/323

Abstract: A method for manufacturing a display device includes forming a first gate metal wire on a substrate, forming a first insulation layer that covers the first gate metal wire, forming a second gate metal wire on the first insulation layer, forming a second main insulation layer that covers the second gate metal wire, forming a second auxiliary insulation layer on the second main insulation layer, forming an exposed portion of an upper surface of the second main insulation layer by polishing the second auxiliary insulation layer, and forming a first data metal wire on the second main insulation layer and the second auxiliary insulation layer.