公开(公告)号：US20240232066A1

公开(公告)日：2024-07-11

申请号：US18454293

申请日：2023-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Won PARK ,  Jooyong PARK ,  Seokmin YOON ,  Bongsoon LIM

IPC: G06F12/02 ,  G06F13/16

CPC classification number: G06F12/023 ,  G06F13/1668

Abstract: Disclosed is a memory system including a memory device and a memory controller. The memory device includes a package of a first memory chip configured to receive input/output signals through first input/output pads and a second memory chip having second input/output pads connected to the first input/output pads by a mapping connection. The memory controller configured to provide the input/output signals to the memory device. The second memory chip is configured to receive input/output signals different from the input/output signals provided by the memory controller to the first memory chip due to the mapping connection. The first and second memory chips are configured to selectively ignore the input/output signals provided by the memory controller based on the mapping connection.

公开(公告)号：US20240170048A1

公开(公告)日：2024-05-23

申请号：US18219369

申请日：2023-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youse KIM ,  Hyunggon KIM ,  Bongsoon LIM

IPC: G11C11/4093 ,  G11C11/408

CPC classification number: G11C11/4093 ,  G11C11/4085 ,  G11C11/4087

Abstract: A nonvolatile memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes word-lines, bit-lines and a memory cell array which includes one or more memory blocks spaced apart from each other, one or more dummy blocks between the one or more memory blocks and a through-hole via region. The second semiconductor layer is under the first semiconductor layer includes a control circuit. The control circuit divides each of the one or more dummy blocks into an adjacent sub-block directly contacting the through-hole via region and a non-adjacent sub-block based on a relative distance from the through-hole via region in the first direction and uses each of the non-adjacent sub-blocks as a sub-block to store data.

公开(公告)号：US20240389330A1

公开(公告)日：2024-11-21

申请号：US18444165

申请日：2024-02-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongseok KWON ,  Jaeduk YU ,  Bongsoon LIM

IPC: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: A semiconductor device is provided. The semiconductor device includes: a first semiconductor structure including a substrate, circuits on the substrate, and a lower interconnection structure electrically connected to the circuits; and a second semiconductor structure including: a plate layer on the first semiconductor structure; gate electrodes and interlayer insulating layers alternately stacked on the plate layer in a first direction that is perpendicular to an upper surface of the plate layer; channel structures passing through the gate electrodes and extending in the first direction; and an upper capacitor structure including an upper gate electrode on the interlayer insulating layers and an upper contact structure extending through the upper gate electrode in the first direction.

公开(公告)号：US20210065828A1

公开(公告)日：2021-03-04

申请号：US16940935

申请日：2020-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeduk YU ,  Bongsoon LIM ,  Yonghyuk CHOI

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/30 ,  G11C16/26 ,  G11C16/32

Abstract: A memory device, a memory system, and/or a method of operating a memory system includes measuring, using processing circuitry, an erase program interval (EPI) of a memory group included in a non-volatile memory (NVM), the EPI being a time period from an erase time point to a program time point of the memory group, determining, using the processing circuitry, a plurality of program modes based on a number of data bits stored in each memory cell of the memory group, selecting, using the processing circuitry, a program mode for the memory group from the plurality of program modes, based on the measured EPI of the memory group, and performing, using the processing circuitry, a program operation on the memory group corresponding to the selected program mode.

公开(公告)号：US20230116928A1

公开(公告)日：2023-04-20

申请号：US17742874

申请日：2022-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwon PARK ,  Bongsoon LIM ,  Byungsoo KIM

IPC: G11C16/16 ,  G11C16/26 ,  G11C16/08 ,  G11C16/30 ,  G11C5/06

Abstract: A non-volatile memory device includes a plurality of word lines stacked above a substrate in a vertical direction; erase control lines that are spaced apart from each other in a first direction and extend in a second direction; a pass transistor circuit including a first pass transistor connected to a first group of erase control lines and a second pass transistor connected to a second group of erase control lines; and a memory cell array including a plurality of blocks. The first group of erase control lines are relatively close to a word line cut region and the second group of erase control lines are relatively far from the word line cut region. Each of the plurality of blocks includes a plurality of channel structures connected to the word lines and the erase control lines and each channel structure extends in the vertical direction.

公开(公告)号：US20230027955A1

公开(公告)日：2023-01-26

申请号：US17697386

申请日：2022-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bongsoon LIM ,  Hyunggon KIM

IPC: H01L27/11582 ,  H01L27/11573 ,  G11C16/04 ,  G11C16/06

Abstract: A non-volatile memory device includes a memory cell region and a peripheral circuit region below the memory cell region in a vertical direction. The memory cell region includes an upper substrate, channel structures extending in the vertical direction, and a first upper metal line extending in a first direction. The peripheral circuit region includes a first lower metal line extending in a second direction and a first via structure on the first lower metal line and a second via structure on the first lower metal line, a top surface of the second via being in contact with the upper substrate. The memory cell region further includes a first through-hole via structure passing through the upper substrate and the first via structure, and electrically connecting the first upper metal line to the first lower metal line; and the first upper metal line is electrically connected to the upper substrate through the first through-hole via structure, the first lower metal line, and the second via structure.

公开(公告)号：US20220075565A1

公开(公告)日：2022-03-10

申请号：US17455037

申请日：2021-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk CHOI ,  Jaeduk YU ,  Sangwan NAM ,  Sangwon PARK ,  Daeseok BYEON ,  Bongsoon LIM

IPC: G06F3/06 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04

Abstract: A nonvolatile memory device includes a first semiconductor layer including an upper substrate in which word-lines extending in a first direction and bit-lines extending in a second direction are disposed and a memory cell array, a second semiconductor layer, a control circuit, and a pad region. The memory cell array includes a vertical structure on the upper substrate, and the vertical structure includes memory blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The vertical structure includes via areas in which one or more through-hole vias are provided, and the via areas are spaced apart in the second direction. The memory cell array includes mats corresponding to different bit-lines of the bit-lines. At least two of the mats include a different number of the via areas according to a distance from the pad region in the first direction.

公开(公告)号：US20210064295A1

公开(公告)日：2021-03-04

申请号：US16891457

申请日：2020-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeduk YU ,  Bongsoon LIM ,  Yonghyuk CHOI

IPC: G06F3/06

Abstract: A memory device, a memory system, and/or a method of operating a memory system includes measuring, using processing circuitry, an erase program interval (EPI) of a memory group included in a non-volatile memory (NVM), the EPI being a time period from an erase time point to a program time point of the memory group, determining, using the processing circuitry, a plurality of program modes based on a number of data bits stored in each memory cell of the memory group, selecting, using the processing circuitry, a program mode for the memory group from the plurality of program modes, based on the measured EPI of the memory group, and performing, using the processing circuitry, a program operation on the memory group corresponding to the selected program mode.

公开(公告)号：US20240194269A1

公开(公告)日：2024-06-13

申请号：US18517429

申请日：2023-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungsoo KIM ,  Yohan LEE ,  Hyunggon KIM ,  Sang Soo PARK ,  Bongsoon LIM ,  Jin-Young CHUN

IPC: G11C16/16 ,  G11C16/04

CPC classification number: G11C16/16 ,  G11C16/0483

Abstract: A memory device includes a memory cell array having a plurality of memory blocks therein, including a target memory block. A voltage generator is provided, which is configured to generate an erase voltage and row line voltages, which are provided to the target memory block upon which an erase operation is to be performed. Control logic is provided, which is configured to control the memory cell array and the voltage generator. In addition, during operation, the erase voltage is provided to at least one of a bitline or a common source line associated with the target memory block, and a gate line of a transistor provided with the erase voltage is precharged before the erase voltage is provided to the at least one of the bitline or the common source line of the target memory block.

公开(公告)号：US20240130131A1

公开(公告)日：2024-04-18

申请号：US18301575

申请日：2023-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeawon JEONG ,  Dongha SHIN ,  Bongsoon LIM

IPC: H10B43/35 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/35 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27

Abstract: A memory device may include word line patterns stacked on a substrate and spaced from each other in a vertical direction, a channel structure extending in the vertical direction, and first contact plugs and second contact plugs extending in the vertical direction. The substrate may include a cell area, a cell wiring area, and a through-hole wiring area. The word line patterns may be on the cell area and the cell wiring area and may extend to the cell wiring area in a direction parallel to an upper surface of the substrate. The first contact plugs may be on the cell wiring area and each may be electrically connected with a corresponding one of the word line patterns and insulated from remaining word line patterns other than the corresponding one of the word line patterns. The second contact plugs may be on the through-hole wiring area.