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公开(公告)号：US10249820B2
公开(公告)日：2019-04-02
申请号：US15366574
申请日：2016-12-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kwang-Woo Lee , Dae-Hwan Kang , Gwan-Hyeob Koh
Abstract: The semiconductor device includes a plurality of first conductive patterns on a substrate, a first selection pattern on each of the plurality of first conductive patterns, a first structure on the first selection pattern, a plurality of second conductive patterns on the first structures, a second selection pattern on each of the plurality of second conductive patterns, a second structure on the second selection pattern, and a plurality of third conductive patterns on the second structures. Each of the plurality of first conductive patterns may extend in a first direction. The first structure may include a first variable resistance pattern and a first heating electrode. The first variable resistance pattern and the first heating electrode may contact each other to have a first contact area therebetween. Each of the plurality of second conductive patterns may extend in a second direction crossing the first direction. The second structure may include a second variable resistance pattern and a second heating electrode. The second variable resistance pattern and the second heating electrode may contact each other to have a second contact area therebetween, and the second contact area may be different from the first contact area.
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公开(公告)号：US20180247978A1
公开(公告)日：2018-08-30
申请号：US15964493
申请日：2018-04-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： KYU-RIE SIM , Gwan-Hyeob Koh , Dae-Hwan Kang
CPC classification number: H01L27/2481 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1608 , H01L45/1675
Abstract: The inventive concept provides a memory device, in which memory cells are arranged to have a low variation in electrical characteristics and thereby enhanced reliability, an electronic apparatus including the memory device, and a method of manufacturing the memory device. In the memory device, memory cells at different levels may be covered with spacers having different thicknesses, and this may control resistance characteristics (e.g., set resistance) of the memory cells and to reduce a vertical variation in electrical characteristics of the memory cells. Furthermore, by adjusting the thicknesses of the spacers, a sensing margin of the memory cells may increase.
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公开(公告)号：US20170244031A1
公开(公告)日：2017-08-24
申请号：US15296423
申请日：2016-10-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： JI-HYUN Jeong , Jin-Woo Lee , Gwan-Hyeob Koh , Dae-Hwan Kang
CPC classification number: H01L45/144 , H01L27/2427 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/16 , H01L45/1675 , H01L45/1683
Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.
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公开(公告)号：US20180342672A1
公开(公告)日：2018-11-29
申请号：US16055512
申请日：2018-08-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyu-Rie SIM , Dae-Hwan Kang , Gwan-Hyeob Koh
CPC classification number: H01L45/1233 , H01L27/2427 , H01L27/2481 , H01L43/08 , H01L43/10 , H01L45/04 , H01L45/06 , H01L45/126 , H01L45/1293 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1608 , H01L45/1675
Abstract: A variable resistance memory device includes first memory cells and second memory cells. The first memory cells are between first and second conductive lines, and at areas at which the first and second conductive lines overlap. The second memory cells are between the second and third conductive lines, and at areas at which the second and third conductive lines overlap. Each first memory cell includes a first variable resistance pattern and a first selection pattern. Each second memory cell includes a second variable resistance pattern and a second selection pattern. At least one of the second memory cells is shifted from a closest one of the first memory cells.
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公开(公告)号：US11349074B2
公开(公告)日：2022-05-31
申请号：US17009004
申请日：2020-09-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ji-Hyun Jeong , Jin-Woo Lee , Gwan-Hyeob Koh , Dae-Hwan Kang
Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.
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Patent Agency Ranking
公开(公告)号：US10804466B2
公开(公告)日：2020-10-13
申请号：US16743594
申请日：2020-01-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ji-Hyun Jeong , Jin-Woo Lee , Gwan-Hyeob Koh , Dae-Hwan Kang
Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.
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公开(公告)号：US10593874B2
公开(公告)日：2020-03-17
申请号：US16055512
申请日：2018-08-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyu-Rie Sim , Dae-Hwan Kang , Gwan-Hyeob Koh
Abstract: A variable resistance memory device includes first memory cells and second memory cells. The first memory cells are between first and second conductive lines, and at areas at which the first and second conductive lines overlap. The second memory cells are between the second and third conductive lines, and at areas at which the second and third conductive lines overlap. Each first memory cell includes a first variable resistance pattern and a first selection pattern. Each second memory cell includes a second variable resistance pattern and a second selection pattern. At least one of the second memory cells is shifted from a closest one of the first memory cells.
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公开(公告)号：US10546999B2
公开(公告)日：2020-01-28
申请号：US15346751
申请日：2016-11-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Masayuki Terai , Dae-Hwan Kang , Gwan-Hyeob Koh
IPC: H01L45/00
Abstract: A variable resistance memory device and a method of manufacturing the same, the device including first conductive lines disposed in a first direction on a substrate, each of the first conductive lines extending in a second direction crossing the first direction, and the first and second directions being parallel to a top surface of the substrate; second conductive lines disposed in the second direction over the first conductive lines, each of the second conductive lines extending in the first direction; a memory unit between the first and second conductive lines, the memory unit being in each area overlapping the first and second conductive lines in a third direction substantially perpendicular to the top surface of the substrate, and the memory unit including a variable resistance pattern; and an insulation layer structure between the first and second conductive lines, the insulation layer structure covering the memory unit and including an air gap in at least a portion of an area overlapping neither the first conductive lines nor the second conductive lines in the third direction.
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9.发明申请公开(公告)号：US20190140022A1
公开(公告)日：2019-05-09
申请号：US16135315
申请日：2018-09-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： JI-HYUN JEONG , Dae-Hwan Kang , Du-Eung Kim , Kwang-Jin Lee
Abstract: A memory device includes a first word line extending in a first direction on a substrate, a first bit line extending in a second direction on the first word line, a first memory cell disposed between the first word line and the first bit line, a second word line extending in the first direction on the first bit line, a second bit line extending in the second direction on the second word line, a second memory cell disposed between the second word line and the second bit line, and a first bit line connection structure connected to the first bit line and the second bit line. The first bit line connection structure includes a first bit line contact connected to the first bit line and a second bit line contact, which is connected to the second bit line and vertically overlaps the first bit line contact.
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公开(公告)号：US09716129B1
公开(公告)日：2017-07-25
申请号：US15285922
申请日：2016-10-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyu-Rie Sim , Gwan-Hyeob Koh , Dae-Hwan Kang
CPC classification number: H01L27/2481 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1608 , H01L45/1675
Abstract: The inventive concept provides a memory device, in which memory cells are arranged to have a low variation in electrical characteristics and thereby enhanced reliability, an electronic apparatus including the memory device, and a method of manufacturing the memory device. In the memory device, memory cells at different levels may be covered with spacers having different thicknesses, and this may control resistance characteristics (e.g., set resistance) of the memory cells and to reduce a vertical variation in electrical characteristics of the memory cells. Furthermore, by adjusting the thicknesses of the spacers, a sensing margin of the memory cells may increase.
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