公开(公告)号：US09755074B2

公开(公告)日：2017-09-05

申请号：US14953769

申请日：2015-11-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Yup Chung ,  Hee-Soo Kang ,  Hee-Don Jeong ,  Se-Wan Park

IPC: H01L29/78 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L27/0886 ,  H01L29/785

Abstract: A semiconductor device includes a first multi-channel active pattern, a field insulation layer disposed on the first multi-channel active pattern and including a first region and a second region, the first region having a top surface protruding from a top surface of the second region to a top surface of the first multi-channel active pattern, a first gate electrode crossing the first multi-channel active pattern, the first gate electrode being disposed on the field insulation layer, and a first source or drain disposed between the first gate electrode and the first region of the field insulation layer and including a first facet, the first facet being disposed adjacent to the first region of the field insulation layer at a point lower than the top surface of the first multi-channel active pattern.

公开(公告)号：US10032886B2

公开(公告)日：2018-07-24

申请号：US15170230

申请日：2016-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Yup Chung ,  Hyun-Jo Kim ,  Seong-Yul Park ,  Se-Wan Park ,  Jong-Mil Youn ,  Jeong-Hyo Lee ,  Hwa-Sung Rhee ,  Hee-Don Jeong ,  Ji-Yong Ha

IPC: H01L21/02 ,  H01L29/66 ,  H01L27/092 ,  H01L29/08 ,  H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/165

Abstract: A semiconductor device includes a fin-type pattern including a first short side and a second short side opposed to each other, a first trench in contact with the first short side, a second trench in contact with the second short side, a first field insulating film in the first trench, the first field insulating film including a first portion and a second portion arranged sequentially from the first short side, and a height of the first portion being different from a height of the second portion, a second field insulating film in the second trench, and a first dummy gate on the first portion of the first field insulating film.

公开(公告)号：US09299811B2

公开(公告)日：2016-03-29

申请号：US14519771

申请日：2014-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wook-Je Kim ,  Jae-Yup Chung ,  Jong-Seo Hong ,  Cheol Kim ,  Hee-Soo Kang ,  Hyun-Jo Kim ,  Hee-Don Jeong ,  Soo-Hun Hong ,  Sang-Bom Kang ,  Myeong-Cheol Kim ,  Young-Su Chung

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: Semiconductor devices may include first and second fins that protrude from a substrate, extend in a first direction, and are separated from each other in the first direction. Semiconductor devices may also include a field insulating layer that is disposed between the first and second fins to extend in a second direction intersecting the first direction, an etch-stop layer pattern that is formed on the field insulating layer and a dummy gate structure that is formed on the etch-stop layer pattern.

Abstract translation: 半导体器件可以包括从基板突出的第一和第二鳍片，沿第一方向延伸，并且在第一方向上彼此分离。 半导体器件还可以包括场绝缘层，其设置在第一和第二鳍之间，沿与第一方向相交的第二方向延伸，形成在场绝缘层上的蚀刻停止层图案和伪栅极结构， 形成在蚀刻停止层图案上。

公开(公告)号：US20150147860A1

公开(公告)日：2015-05-28

申请号：US14519771

申请日：2014-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wook-Je Kim ,  Jae-Yup Chung ,  Jong-Seo Hong ,  Cheol Kim ,  Hee-Soo Kang ,  Hyun-Jo Kim ,  Hee-Don Jeong ,  Soo-Hun Hong ,  Sang-Bom Kang ,  Myeong-Cheol Kim ,  Young-Su Chung

IPC: H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: Semiconductor devices may include first and second fins that protrude from a substrate, extend in a first direction, and are separated from each other in the first direction. Semiconductor devices may also include a field insulating layer that is disposed between the first and second fins to extend in a second direction intersecting the first direction, an etch-stop layer pattern that is formed on the field insulating layer and a dummy gate structure that is formed on the etch-stop layer pattern.

Abstract translation: 半导体器件可以包括从基板突出的第一和第二鳍片，沿第一方向延伸，并且在第一方向上彼此分离。 半导体器件还可以包括场绝缘层，其设置在第一和第二鳍之间，沿与第一方向相交的第二方向延伸，形成在场绝缘层上的蚀刻停止层图案和伪栅极结构， 形成在蚀刻停止层图案上。

公开(公告)号：US09627542B2

公开(公告)日：2017-04-18

申请号：US15144662

申请日：2016-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung-Ho Kwon ,  Cheol Kim ,  Ho-Young Kim ,  Se-Jung Park ,  Myeong-Cheol Kim ,  Bo-Kyeong Kang ,  Bo-Un Yoon ,  Jae-Kwang Choi ,  Si-Young Choi ,  Suk-Hoon Jeong ,  Geum-Jung Seong ,  Hee-Don Jeong ,  Yong-Joon Choi ,  Ji-Eun Han

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/423 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8238 ,  H01L29/49

CPC classification number: H01L29/7853 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

公开(公告)号：US10205023B2

公开(公告)日：2019-02-12

申请号：US15694150

申请日：2017-09-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Yup Chung ,  Hee-Soo Kang ,  Hee-Don Jeong ,  Se-Wan Park

IPC: H01L29/78 ,  H01L27/088

Abstract: A semiconductor device includes a first multi-channel active pattern, a field insulation layer disposed on the first multi-channel active pattern and including a first region and a second region, the first region having a top surface protruding from a top surface of the second region to a top surface of the first multi-channel active pattern, a first gate electrode crossing the first multi-channel active pattern, the first gate electrode being disposed on the field insulation layer, and a first source or drain disposed between the first gate electrode and the first region of the field insulation layer and including a first facet, the first facet being disposed adjacent to the first region of the field insulation layer at a point lower than the top surface of the first multi-channel active pattern.

公开(公告)号：US20170365716A1

公开(公告)日：2017-12-21

申请号：US15694150

申请日：2017-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Yup Chung ,  Hee-Soo Kang ,  Hee-Don Jeong ,  Se-Wan Park

IPC: H01L29/78 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L27/0886 ,  H01L29/785

Abstract: A semiconductor device includes a first multi-channel active pattern, a field insulation layer disposed on the first multi-channel active pattern and including a first region and a second region, the first region having a top surface protruding from a top surface of the second region to a top surface of the first multi-channel active pattern, a first gate electrode crossing the first multi-channel active pattern, the first gate electrode being disposed on the field insulation layer, and a first source or drain disposed between the first gate electrode and the first region of the field insulation layer and including a first facet, the first facet being disposed adjacent to the first region of the field insulation layer at a point lower than the top surface of the first multi-channel active pattern.