公开(公告)号：US10083978B2

公开(公告)日：2018-09-25

申请号：US15867974

申请日：2018-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Won Kim ,  Bong-Tae Park ,  Ho-Jun Seong ,  Jae-Hwang Sim ,  Jung-Hoon Jun

IPC: H01L29/788 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/1157 ,  H01L27/11534 ,  H01L27/11524 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/28 ,  H01L27/11573 ,  H01L21/311 ,  H01L21/027 ,  H01L21/265 ,  H01L21/3213

CPC classification number: H01L27/1157 ,  H01L21/0273 ,  H01L21/26513 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/11524 ,  H01L27/11534 ,  H01L27/11573 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/4966 ,  Y02E10/50

Abstract: A method of forming a nonvolatile memory device includes forming first, second, and third gate structures, with the second and third gate structures including first and second spacer structures formed on a sidewall of the second gate structure and sidewalls of the third gate structure. Impurity regions are formed through ion implantation and the first spacer structure shields the second and third gate structures during ion implantation. The second spacer structure defines resulting impurity regions.

公开(公告)号：US20180061843A1

公开(公告)日：2018-03-01

申请号：US15472720

申请日：2017-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Won Kim ,  Bong-Tae Park ,  Ho-Jun Seong ,  Jae-Hwang Sim ,  Jung-Hoon Jun

IPC: H01L27/1157 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/027 ,  H01L27/11573 ,  H01L29/49 ,  H01L27/11524 ,  H01L27/11534

CPC classification number: H01L27/1157 ,  H01L21/0273 ,  H01L21/26513 ,  H01L21/28088 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/11524 ,  H01L27/11534 ,  H01L27/11573 ,  H01L29/4966

Abstract: A method of forming a nonvolatile memory device includes forming first, second, and third gate structures, with the second and third gate structures including first and second spacer structures formed on a sidewall of the second gate structure and sidewalls of the third gate structure. Impurity regions are formed through ion implantation and the first spacer structure shields the second and third gate structures during ion implantation. The second spacer structure defines resulting impurity regions.

公开(公告)号：US20180138188A1

公开(公告)日：2018-05-17

申请号：US15867974

申请日：2018-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Won Kim ,  Bong-Tae Park ,  Ho-Jun Seong ,  Jae-Hwang Sim ,  Jung-Hoon Jun

IPC: H01L27/1157 ,  H01L27/11534 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/28 ,  H01L27/11573 ,  H01L21/311 ,  H01L21/027 ,  H01L21/265 ,  H01L21/3213 ,  H01L27/11524

CPC classification number: H01L27/1157 ,  H01L21/0273 ,  H01L21/26513 ,  H01L21/28088 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/11524 ,  H01L27/11534 ,  H01L27/11573 ,  H01L29/4966

Abstract: A method of forming a nonvolatile memory device includes forming first, second, and third gate structures, with the second and third gate structures including first and second spacer structures formed on a sidewall of the second gate structure and sidewalls of the third gate structure. Impurity regions are formed through ion implantation and the first spacer structure shields the second and third gate structures during ion implantation. The second spacer structure defines resulting impurity regions.

公开(公告)号：US09793155B2

公开(公告)日：2017-10-17

申请号：US14734287

申请日：2015-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jun Seong ,  Jee-hoon Han

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/28 ,  H01L21/3213 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11531 ,  H01L21/033 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

CPC classification number: H01L21/768 ,  H01L21/0337 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/32139 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11531 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: A method of fabricating a memory device includes forming an etching object layer and a lower sacrificial layer on a substrate, and forming an upper sacrificial pattern structure on the lower sacrificial layer. The upper sacrificial pattern structure includes a pad portion and a line portion on the lower sacrificial layer. An upper spacer is formed by covering a side wall of the upper sacrificial pattern structure. A lower sacrificial pattern structure including a lower sacrificial pad portion and a lower sacrificial line portion is formed by etching the lower sacrificial layer, by using the upper sacrificial pad portion and the upper spacer as a mask. A lower spacer layer is formed by covering the lower sacrificial pattern structure. A lower mask pattern including at least one line mask, bridge mask, and pad mask, is formed by etching the lower spacer layer and the lower sacrificial pattern structure.

公开(公告)号：US09905569B1

公开(公告)日：2018-02-27

申请号：US15472720

申请日：2017-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Won Kim ,  Bong-Tae Park ,  Ho-Jun Seong ,  Jae-Hwang Sim ,  Jung-Hoon Jun

IPC: H01L21/8234 ,  H01L27/1157 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/265 ,  H01L21/027 ,  H01L27/11573 ,  H01L29/49 ,  H01L27/11524 ,  H01L27/11534

CPC classification number: H01L27/1157 ,  H01L21/0273 ,  H01L21/26513 ,  H01L21/28088 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/11524 ,  H01L27/11534 ,  H01L27/11573 ,  H01L29/4966

Abstract: A method of forming a nonvolatile memory device includes forming first, second, and third gate structures, with the second and third gate structures including first and second spacer structures formed on a sidewall of the second gate structure and sidewalls of the third gate structure. Impurity regions are formed through ion implantation and the first spacer structure shields the second and third gate structures during ion implantation. The second spacer structure defines resulting impurity regions.

公开(公告)号：US08962422B2

公开(公告)日：2015-02-24

申请号：US13804398

申请日：2013-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jun Seong ,  Jae-Hwang Sim

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788 ,  H01L27/115 ,  H01L49/02 ,  H01L27/06

CPC classification number: H01L29/66477 ,  H01L21/28273 ,  H01L27/0629 ,  H01L27/11521 ,  H01L28/20 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of fabricating a semiconductor device includes etching a substrate to form a field trench defining an active region and a lower gate pattern on the active region, the lower gate pattern including a tunneling insulating pattern and a lower gate electrode pattern, filling a field insulating material in the field trench to form a field region, forming an upper gate pattern on the lower gate pattern, sequentially forming a stopping layer and a buffer layer on the field region and the upper gate pattern, forming a first resistive pattern on the buffer layer of the field region, and forming a second resistive pattern on the buffer layer on the upper gate pattern, forming an interlayer insulating layer covering the first and second resistive patterns, and performing a planarization process to remove a top surface of the interlayer insulating layer and to remove the second resistive pattern.

Abstract translation: 一种制造半导体器件的方法包括蚀刻衬底以形成在有源区上限定有源区和下栅极图案的场沟槽，下栅极图案包括隧道绝缘图案和下栅极电极图案，填充场绝缘 在沟槽中形成场区域，在下栅极图案上形成上栅极图案，在场区域和上栅极图案上依次形成停止层和缓冲层，在缓冲层上形成第一电阻图案 并且在上栅极图案上的缓冲层上形成第二电阻图案，形成覆盖第一和第二电阻图案的层间绝缘层，并执行平面化处理以去除层间绝缘层的顶表面，以及 以去除第二电阻图案。