中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

66 records (took 0.01 seconds)

    COORDINATED IN-MODULE RAS FEATURES FOR SYNCHRONOUS DDR COMPATIBLE MEMORY
    1.
    发明申请
    COORDINATED IN-MODULE RAS FEATURES FOR SYNCHRONOUS DDR COMPATIBLE MEMORY 有权

    公开(公告)号：US20220229551A1

    公开(公告)日：2022-07-21

    申请号：US17713228

    申请日：2022-04-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mu-Tien CHANG ,  Dimin NIU ,  Hongzhong ZHENG ,  Sun Young LIM ,  Indong KIM ,  Jangseok CHOI

    IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52

    Abstract: A memory module includes a memory array, an interface and a controller. The memory array includes an array of memory cells and is configured as a dual in-line memory module (DIMM). The DIMM includes a plurality of connections that have been repurposed from a standard DIMM pin out configuration to interface operational status of the memory device to a host device. The interface is coupled to the memory array and the plurality of connections of the DIMM to interface the memory array to the host device. The controller is coupled to the memory array and the interface and controls at least one of a refresh operation of the memory array, control an error-correction operation of the memory array, control a memory scrubbing operation of the memory array, and control a wear-level control operation of the array, and the controller to interface with the host device.

    HIGH BANDWIDTH MEMORY SYSTEM
    2.
    发明申请
    HIGH BANDWIDTH MEMORY SYSTEM 审中-公开

    公开(公告)号：US20200349093A1

    公开(公告)日：2020-11-05

    申请号：US16569657

    申请日：2019-09-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Krishna T. MALLADI ,  Dimin NIU ,  Hongzhong ZHENG

    IPC: G06F13/16 ,  G06F12/06

    Abstract: A high-bandwidth memory (HBM) includes a memory and a controller. The controller receives a data write request from a processor external to the HBM and the controller stores an entry in the memory indicating at least one address of data of the data write request and generates an indication that a data bus is available for an operation during a cycle time of the data write request based on the data write request comprising sparse data or data-value similarity. Sparse data includes a predetermined percentage of data values equal to zero, and data-value similarity includes a predetermined amount of spatial value locality of the data values. The predetermined percentage of data values equal to zero of sparse data and the predetermined amount of spatial value locality of the special-value pattern are both based on a predetermined data granularity.

    DATAFLOW ACCELERATOR ARCHITECTURE FOR GENERAL MATRIX-MATRIX MULTIPLICATION AND TENSOR COMPUTATION IN DEEP LEARNING
    3.
    发明申请
    DATAFLOW ACCELERATOR ARCHITECTURE FOR GENERAL MATRIX-MATRIX MULTIPLICATION AND TENSOR COMPUTATION IN DEEP LEARNING 审中-公开

    公开(公告)号：US20200183837A1

    公开(公告)日：2020-06-11

    申请号：US16388863

    申请日：2019-04-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Peng GU ,  Krishna MALLADI ,  Hongzhong ZHENG ,  Dimin NIU

    IPC: G06F12/0802 ,  G06F17/16

    Abstract: A tensor computation dataflow accelerator semiconductor circuit is disclosed. The data flow accelerator includes a DRAM bank and a peripheral array of multiply-and-add units disposed adjacent to the DRAM bank. The peripheral array of multiply-and-add units are configured to form a pipelined dataflow chain in which partial output data from one multiply-and-add unit from among the array of multiply-and-add units is fed into another multiply-and-add unit from among the array of multiply-and-add units for data accumulation. Near-DRAM-processing dataflow (NDP-DF) accelerator unit dies may be stacked atop a base die. The base die may be disposed on a passive silicon interposer adjacent to a processor or a controller. The NDP-DF accelerator units may process partial matrix output data in parallel. The partial matrix output data may be propagated in a forward or backward direction. The tensor computation dataflow accelerator may perform a partial matrix transposition.

    DEDUPE DRAM CACHE
    4.
    发明申请
    DEDUPE DRAM CACHE 审中-公开

    公开(公告)号：US20190227941A1

    公开(公告)日：2019-07-25

    申请号：US15934940

    申请日：2018-03-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mu Tien CHANG ,  Andrew CHANG ,  Dongyan JIANG ,  Hongzhong ZHENG

    IPC: G06F12/0891 ,  G06F3/06

    Abstract: A dedupable cache is disclosed. The dedupable cache may include cache memory including both a dedupable read cache and a non-dedupable write buffer. The dedupable cache may also include a deduplication engine to manage reads from and writes to the dedupable read cache, and may return a write status signal indicating whether a write to the dedupable read cache was successful or not. The dedupable cache may also include a cache controller, which may include: a cache hit/miss check to determine whether an address in a request may be found in the dedupable read cache; a hit block to manage data accesses when the requested data may be found in the dedupable read cache; a miss block to manage data accesses when the requested data is not found in the dedupable read cache; and a history storage to store information about accesses to the data in the dedupable read cache.

    DUAL ROW-COLUMN MAJOR DRAM
    5.
    发明申请
    DUAL ROW-COLUMN MAJOR DRAM 审中-公开

    公开(公告)号：US20190043553A1

    公开(公告)日：2019-02-07

    申请号：US15713587

    申请日：2017-09-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mu-Tien CHANG ,  Dimin NIU ,  Hongzhong ZHENG

    IPC: G11C11/408 ,  G06F3/06

    Abstract: A memory device includes an array of 2T1C DRAM cells and a memory controller. The DRAM cells are arranged as a plurality of rows and columns of DRAM cells. The memory controller is internal to the memory device and is coupled to the array of DRAM cells. The memory controller is capable of receiving commands input to the memory device and is responsive to the received commands to control row-major access and column-major access to the array of DRAM cells. In one embodiment, each transistor of a memory cell includes a terminal directly coupled to a storage node of the capacitor. In another embodiment, a first transistor of a memory cell includes a terminal directly coupled to a storage node of the capacitor, and a second transistor of the 2T1C memory cell includes a gate terminal directly coupled to the storage node of the capacitor.

    SOFTWARE STACK AND PROGRAMMING FOR DPU OPERATIONS
    6.
    发明申请
    SOFTWARE STACK AND PROGRAMMING FOR DPU OPERATIONS 审中-公开

    公开(公告)号：US20180121130A1

    公开(公告)日：2018-05-03

    申请号：US15426015

    申请日：2017-02-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Shaungchen LI ,  Dimin NIU ,  Krishna MALLADI ,  Hongzhong ZHENG

    IPC: G06F3/06 ,  G11C11/4094

    CPC classification number: G06F3/0647 ,  G06F3/061 ,  G06F3/0683 ,  G11C7/1006 ,  G11C11/405 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

    Abstract: A system includes a library, a compiler, a driver and at least one dynamic random access memory (DRAM) processing unit (DPU). The library may determine at least one DPU operation corresponding to a received command. The compiler may form at least one DPU instruction for the DPU operation. The driver may send the at least one DPU instruction to at least one DPU. The DPU may include at least one computing cell array that includes a plurality of DRAM-based computing cells arranged in an array having at least one column in which the at least one column may include at least three rows of DRAM-based computing cells configured to provide a logic function that operates on a first row and a second row of the at least three rows and configured to store a result of the logic function in a third row of the at least three rows.

    RECONFIGURABLE LOGIC ARCHITECTURE
    9.
    发明申请
    RECONFIGURABLE LOGIC ARCHITECTURE 有权
    可重构逻辑架构

    公开(公告)号：US20160173101A1

    公开(公告)日：2016-06-16

    申请号：US14838347

    申请日：2015-08-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mingyu GAO ,  Hongzhong ZHENG ,  Krishna T. MALLADI ,  Robert BRENNAN

    IPC: H03K19/177 ,  H01L25/00 ,  H01L25/18

    CPC classification number: H03K19/1776 ,  H01L25/18 ,  H01L25/50 ,  H01L2924/0002 ,  H03K19/17728 ,  H03K19/17736 ,  H01L2924/00

    Abstract: According to one general aspect, an apparatus may include a plurality of stacked integrated circuit dies. The dies may include a memory cell die configured to store data in a random access fashion. The dies may also include a look-up table die comprising a random access memory array that, in turn, includes a reconfigurable look-up table. The reconfigurable look-up table may be configured to perform a logic function. The reconfigurable look-up table may include a plurality of random access memory cells configured to store a look-up table to perform a logic function, and a local row decoder configured to activate one or more rows of memory cells based upon a set of input signals. The look-up table stored in the plurality of memory cells may be configured to be dynamically altered via a memory write operation to the random access memory array.

    Abstract translation: 根据一个一般方面，一种装置可以包括多个堆叠的集成电路管芯。 管芯可以包括被配置为以随机存取方式存储数据的存储单元管芯。 模具还可以包括查找表模具，其包括随机存取存储器阵列，其又包括可重新配置的查找表。 可重构查找表可以被配置为执行逻辑功能。 可配置查找表可以包括被配置为存储查询表以执行逻辑功能的多个随机存取存储器单元，以及配置成基于一组输入来激活一行或多行存储器单元的本地行解码器 信号。 存储在多个存储器单元中的查找表可以被配置为通过存储器写入操作来动态地改变到随机存取存储器阵列。

    HETEROGENEOUS ACCELERATOR FOR HIGHLY EFFICIENT LEARNING SYSTEMS
    10.
    发明公开
    HETEROGENEOUS ACCELERATOR FOR HIGHLY EFFICIENT LEARNING SYSTEMS 审中-公开

    公开(公告)号：US20240193111A1

    公开(公告)日：2024-06-13

    申请号：US18444619

    申请日：2024-02-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Krishna T. MALLADI ,  Hongzhong ZHENG

    IPC: G06F13/28 ,  G06F9/445 ,  G06F9/48 ,  G06F15/76

    CPC classification number: G06F13/28 ,  G06F9/445 ,  G06F9/4806 ,  G06F2015/768

    Abstract: An apparatus may include a heterogeneous computing environment that may be controlled, at least in part, by a task scheduler in which the heterogeneous computing environment may include a processing unit having fixed logical circuits configured to execute instructions; a reprogrammable processing unit having reprogrammable logical circuits configured to execute instructions that include instructions to control processing-in-memory functionality; and a stack of high-bandwidth memory dies in which each may be configured to store data and to provide processing-in-memory functionality controllable by the reprogrammable processing unit such that the reprogrammable processing unit is at least partially stacked with the high-bandwidth memory dies. The task scheduler may be configured to schedule computational tasks between the processing unit, and the reprogrammable processing unit.

Patent Agency Ranking