公开(公告)号：US20210143008A1

公开(公告)日：2021-05-13

申请号：US16905310

申请日：2020-06-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungmin Ko ,  Hyeongmun Kang ,  Sangsick Park ,  Hyeonjun Song

IPC: H01L21/02 ,  H01L21/56 ,  H01L21/762

Abstract: A semiconductor package includes a buffer, a chip stack mounted on the buffer, an adhesive layer disposed between the buffer and the chip stack, and a molding material surrounding the chip stack. The buffer includes a plurality of trenches disposed adjacent to a plurality of edges of the buffer. Each of the trenches is shorter than a corresponding adjacent edge of a chip area of the buffer.

公开(公告)号：US11756935B2

公开(公告)日：2023-09-12

申请号：US17352757

申请日：2021-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Insup Shin ,  Hyeongmun Kang ,  Jungmin Ko ,  Hwanyoung Choi

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: A chip-stacked semiconductor package includes: a base chip having a base through via; a first chip stacked on the base chip in an offset form, wherein the first chip has a first exposed surface and a first through via electrically connected to the base through via; a first molding layer positioned on the base chip and covering a first non-exposed surface, facing the first exposed surface, of the first chip; a second chip stacked on the first chip in an offset form, wherein the second chip has a second exposed surface and a second through via electrically connected to the first through via; and a second molding layer formed on the first chip and covering a second non-exposed surface, facing the second exposed surface, of the second chip.

公开(公告)号：US12230575B2

公开(公告)日：2025-02-18

申请号：US17517798

申请日：2021-11-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeongmun Kang ,  Woodong Lee ,  Insup Shin ,  Youngwoo Lim

IPC: H01L23/538 ,  H01L25/065

Abstract: A carrier structure including semiconductor chip stack structures; and a carrier tape including a plurality of pockets respectively accommodating the semiconductor chip stack structures, wherein each of the plurality of pockets includes a bottom surface, first sidewalls in four corner regions of each of the plurality of pockets, and second sidewalls between adjacent first sidewalls, each of the first sidewalls has a first portion having a first inclination angle and a second portion on the first portion and having a second inclination angle, the second inclination angle being greater than the first inclination angle, and vertices of lower surfaces of the semiconductor chip stack structures are in contact with the first sidewalls.

公开(公告)号：US11469099B2

公开(公告)日：2022-10-11

申请号：US16905310

申请日：2020-06-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungmin Ko ,  Hyeongmun Kang ,  Sangsick Park ,  Hyeonjun Song

IPC: G11C5/06 ,  H01L27/108 ,  H01L21/02 ,  H01L21/56 ,  H01L21/762

Abstract: A semiconductor package includes a buffer, a chip stack mounted on the buffer, an adhesive layer disposed between the buffer and the chip stack, and a molding material surrounding the chip stack. The buffer includes a plurality of trenches disposed adjacent to a plurality of edges of the buffer. Each of the trenches is shorter than a corresponding adjacent edge of a chip area of the buffer.

公开(公告)号：US09035308B2

公开(公告)日：2015-05-19

申请号：US14197203

申请日：2014-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin Yim ,  Hyeongmun Kang ,  Taesung Park ,  Eunchul Ahn

IPC: H01L23/58 ,  G01R31/26 ,  H01L23/544 ,  H01L21/3105

CPC classification number: H01L23/544 ,  H01L21/3105 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package, comprising: a semiconductor substrate; a mold layer on the semiconductor substrate; and a marking formed on a surface of the mold layer, the marking comprising dot markings substantially discontinuously arranged in vertical and horizontal directions of a display region. An effective area of the dot markings within a unit display region of the marking is smaller than about half a total area of the unit display region.

Abstract translation: 一种半导体封装，包括：半导体衬底; 半导体衬底上的模具层; 以及形成在所述模具层的表面上的标记，所述标记包括基本上不连续地布置在显示区域的垂直和水平方向上的点标记。 标记的单位显示区域内的点标记的有效面积小于单位显示区域的总面积的约一半。

公开(公告)号：US20220278010A1

公开(公告)日：2022-09-01

申请号：US17464002

申请日：2021-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeongmun Kang ,  Taehyeong Kim ,  Woodong Lee ,  Hwanyoung Choi

IPC: H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L21/56

Abstract: A semiconductor package includes a base structure, a lower semiconductor chip disposed on the base structure, an upper semiconductor chip disposed on the lower semiconductor chip, a connecting structure including a lower pad disposed on the lower semiconductor chip, an upper pad disposed under the upper semiconductor chip, and a connecting bump disposed between the lower pad and the upper pad, a dummy chip disposed on the upper semiconductor chip, an upper adhesive layer including an upper adhesive portion disposed between the upper semiconductor chip and the dummy chip, and an upper protrusion portion disposed at opposite sides of the upper adhesive portion, to surround lower portions of opposite side surfaces of the dummy chip, and a molding layer disposed at opposite sides of the dummy chip, to surround upper portions of the opposite side surfaces of the dummy chip and the upper protrusion portion.

公开(公告)号：US11257794B2

公开(公告)日：2022-02-22

申请号：US17030588

申请日：2020-09-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjun Song ,  Eunkyul Oh ,  Hyeongmun Kang ,  Jungmin Ko

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package may include a package substrate, semiconductor chips, signal bumps, and first and second heat dissipation bumps. The semiconductor chips may be stacked on an upper surface of the package substrate, have first and second regions having different heat dissipation efficiencies. The second temperature may be higher than the first temperature. The signal bumps may be arranged between the semiconductor chips. The first heat dissipation bumps may be arranged between the semiconductor chips in the first region by a first pitch. The second heat dissipation bumps may be arranged between the semiconductor chips in the second region by a second pitch narrower than the first pitch. Heat generated from the second region of the semiconductor chips may be dissipated through the second heat dissipation bumps, which may be relatively closely arranged with each other.

公开(公告)号：US11257725B2

公开(公告)日：2022-02-22

申请号：US17010059

申请日：2020-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehyeong Kim ,  Hyeongmun Kang ,  Seungduk Baek

IPC: H01L21/66 ,  H01L23/00 ,  H01L25/18

Abstract: Disclosed is a semiconductor package comprising a first semiconductor chip and at least one second semiconductor chip on the first semiconductor chip. The second semiconductor chip includes first and second test bumps that are adjacent to an edge of the second semiconductor chip and are on a bottom surface of the second semiconductor chip. The first and second test bumps are adjacent to each other. The second semiconductor chip also includes a plurality of data bumps that are adjacent to a center of the second semiconductor chip and are on the bottom surface of the second semiconductor chip. A first interval between the second test bump and one of the data bumps is greater than a second interval between the first test bump and the second test bump. The one of the data bumps is most adjacent to the second test bump.

公开(公告)号：US12125753B2

公开(公告)日：2024-10-22

申请号：US17584776

申请日：2022-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehyeong Kim ,  Hyeongmun Kang ,  Seungduk Baek

IPC: H01L21/66 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

CPC classification number: H01L22/34 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/1412 ,  H01L2224/14515 ,  H01L2224/16148 ,  H01L2224/17132 ,  H01L2224/17133 ,  H01L2224/17515 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: Disclosed is a semiconductor package comprising a first semiconductor chip and at least one second semiconductor chip on the first semiconductor chip. The second semiconductor chip includes first and second test bumps that are adjacent to an edge of the second semiconductor chip and are on a bottom surface of the second semiconductor chip. The first and second test bumps are adjacent to each other. The second semiconductor chip also includes a plurality of data bumps that are adjacent to a center of the second semiconductor chip and are on the bottom surface of the second semiconductor chip. A first interval between the second test bump and one of the data bumps is greater than a second interval between the first test bump and the second test bump. The one of the data bumps is most adjacent to the second test bump.

公开(公告)号：US11721601B2

公开(公告)日：2023-08-08

申请号：US17095210

申请日：2020-11-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeongmun Kang ,  Jungmin Ko ,  Seungduk Baek ,  Taehyeong Kim ,  Insup Shin

IPC: H01L23/24 ,  H01L23/31 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L23/24 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/5385 ,  H01L24/13 ,  H01L2924/1434 ,  H01L2924/3511

Abstract: A semiconductor package includes a substrate, a plurality of semiconductor devices stacked on the substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the substrate and the plurality of semiconductor devices, and molding resin surrounding the plurality of semiconductor devices. At least one of the underfill fillets is exposed from side surfaces of the molding resin.