公开(公告)号：US20240063129A1

公开(公告)日：2024-02-22

申请号：US18299927

申请日：2023-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Geun Ahn ,  Seokhyun Lee ,  Yanggyoo Jung ,  Hwanyoung Choi

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H10B80/00

CPC classification number: H01L23/5383 ,  H01L23/5385 ,  H01L23/49816 ,  H01L24/16 ,  H01L23/3157 ,  H01L23/5384 ,  H10B80/00 ,  H01L2224/16227

Abstract: A semiconductor package includes a package substrate, an interposer substrate on the package substrate, first connection bumps between the package substrate and the interposer substrate, first and second semiconductor chips on the interposer substrate, second connection bumps between the interposer substrate and the first and second semiconductor chips, and an upper molding layer on the interposer substrate and at least partially surrounding the first semiconductor chip and the second semiconductor chip. The interposer substrate includes a plurality of sub-interposers horizontally spaced apart from each other and each including through electrodes, a lower molding layer in a space between the sub-interposers, and a redistribution layer electrically connected to the through electrodes on the sub-interposers and the lower molding layer. A sum of areas of the sub-interposers is less than a sum of areas of the first and second semiconductor chips.

公开(公告)号：US20240063103A1

公开(公告)日：2024-02-22

申请号：US18236090

申请日：2023-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheol Kim ,  Seokhyun Lee ,  Seokgeun Ahn ,  Hwanyoung Choi

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49822 ,  H01L25/105 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/08 ,  H01L24/16 ,  H01L23/3107 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2224/08235 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/1579 ,  H01L2924/15153 ,  H01L2924/15174 ,  H01L2924/15184

Abstract: A semiconductor package includes a first redistribution structure including a top surface, a chip arranged on the top surface of the first redistribution structure the chip having a top surface, bottom surface, and side surfaces, and a package body arranged on the top surface of the first redistribution structure to cover the side surfaces of the chip. The first redistribution structure includes a plurality of redistribution layers stacked in a vertical direction, a plurality of redistribution insulating layers stacked in the vertical direction and which insulate the plurality of redistribution layers from each other, a plurality of redistribution vias buried in a plurality of redistribution via holes penetrating the plurality of redistribution insulating layers and electrically connecting the plurality of redistribution layers to each other, and a plurality of self-formed barrier layers formed between side surfaces of the plurality of redistribution layers and the plurality of redistribution insulating layers.

公开(公告)号：US11756935B2

公开(公告)日：2023-09-12

申请号：US17352757

申请日：2021-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Insup Shin ,  Hyeongmun Kang ,  Jungmin Ko ,  Hwanyoung Choi

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: A chip-stacked semiconductor package includes: a base chip having a base through via; a first chip stacked on the base chip in an offset form, wherein the first chip has a first exposed surface and a first through via electrically connected to the base through via; a first molding layer positioned on the base chip and covering a first non-exposed surface, facing the first exposed surface, of the first chip; a second chip stacked on the first chip in an offset form, wherein the second chip has a second exposed surface and a second through via electrically connected to the first through via; and a second molding layer formed on the first chip and covering a second non-exposed surface, facing the second exposed surface, of the second chip.

公开(公告)号：US20220278010A1

公开(公告)日：2022-09-01

申请号：US17464002

申请日：2021-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeongmun Kang ,  Taehyeong Kim ,  Woodong Lee ,  Hwanyoung Choi

IPC: H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L21/56

Abstract: A semiconductor package includes a base structure, a lower semiconductor chip disposed on the base structure, an upper semiconductor chip disposed on the lower semiconductor chip, a connecting structure including a lower pad disposed on the lower semiconductor chip, an upper pad disposed under the upper semiconductor chip, and a connecting bump disposed between the lower pad and the upper pad, a dummy chip disposed on the upper semiconductor chip, an upper adhesive layer including an upper adhesive portion disposed between the upper semiconductor chip and the dummy chip, and an upper protrusion portion disposed at opposite sides of the upper adhesive portion, to surround lower portions of opposite side surfaces of the dummy chip, and a molding layer disposed at opposite sides of the dummy chip, to surround upper portions of the opposite side surfaces of the dummy chip and the upper protrusion portion.

公开(公告)号：US20240170358A1

公开(公告)日：2024-05-23

申请号：US18378603

申请日：2023-10-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokgeun Ahn ,  Cheol Kim ,  Hwanyoung Choi

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/367 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2225/1058 ,  H01L2924/3511

Abstract: A semiconductor package includes a lower redistribution structure, a first semiconductor chip and a second semiconductor chip that stacked on the lower redistribution structure, the second semiconductor chip including a heat dissipation pad disposed at an upper surface of the second semiconductor chip, a lower conductive pillar disposed on the lower redistribution structure, an upper conductive pillar disposed on the lower conductive pillar, a heat dissipation pillar disposed on the heat dissipation pad, an upper redistribution structure disposed on the upper conductive pillar; and a heat dissipation structure disposed on the heat dissipation pillar.

公开(公告)号：US20240014117A1

公开(公告)日：2024-01-11

申请号：US18117736

申请日：2023-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok Geun AHN ,  Hwanyoung Choi

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/16 ,  H10B80/00

CPC classification number: H01L23/49838 ,  H01L24/32 ,  H01L25/165 ,  H01L25/162 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H10B80/00 ,  H01L2224/32225 ,  H01L2924/1434 ,  H01L2924/1431 ,  H01L2224/13147 ,  H01L2224/16235 ,  H01L2224/73253

Abstract: A semiconductor package includes a first lower redistribution layer, a first upper redistribution layer over the first lower redistribution layer, a first semiconductor chip between the first lower redistribution layer and the first upper redistribution layer, a first connection post spaced apart from the first semiconductor chip and connecting the first lower redistribution layer to the first upper redistribution layer, a first interposition layer on the first upper redistribution layer, a second interposition layer on the first interposition layer, a second lower redistribution layer on the second interposition layer, a second upper redistribution layer over the second lower redistribution layer, a second semiconductor chip between the second lower redistribution layer and the second upper redistribution layer, and a second connection post spaced apart from each other and connecting the second lower redistribution layer to the second upper redistribution layer.

公开(公告)号：US20240014086A1

公开(公告)日：2024-01-11

申请号：US18135541

申请日：2023-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokgeun Ahn ,  Seokhyun Lee ,  Hwanyoung Choi

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/3114 ,  H01L25/0657 ,  H01L23/49838 ,  H01L21/563 ,  H01L24/05 ,  H01L23/5226 ,  H01L24/16 ,  H01L2224/04105 ,  H01L2225/06544 ,  H01L2224/05009 ,  H01L2224/16227 ,  H01L2924/182

Abstract: A semiconductor package includes: a substrate; a circuit layer disposed on a lower surface of the substrate, the circuit layer including an interconnection structure; a first redistribution structure disposed adjacent to the circuit layer, the first redistribution structure including a first redistribution layer; a connection structure including a first connection via electrically connected to the first redistribution layer, a second connection via electrically connected to the interconnection structure, and a connection interconnection interconnecting the first and second connection vias; a semiconductor chip disposed below the first redistribution structure, and electrically connected to the first redistribution layer; a first vertical connection structure disposed on a lower surface of the circuit layer; a second vertical connection structure disposed on a lower surface of the connection structure; and a second redistribution structure disposed below the semiconductor chip and the first and second vertical connection structures.