公开(公告)号：US20190177845A1

公开(公告)日：2019-06-13

申请号：US16039565

申请日：2018-07-19

Applicant: Samsung Electronics Co., Ltd. ,  Tokyo Electron Limited

Inventor： Seung Jae Baek ,  Hyun Namkoong ,  Tae Jong Lee ,  Sun Jung Kim ,  Ju Yeon Kim ,  Noriaki Fukiage ,  Masahide Iwasaki ,  Yuta Sorita

IPC: C23C16/455 ,  H01L21/687 ,  C23C16/50 ,  C23C16/458

Abstract: A semiconductor process chamber is provided. The semiconductor process chamber includes a susceptor on which a plurality of wafers are disposed; a showerhead structure opposing the susceptor and disposed to be spaced apart from the susceptor; a plurality of plates opposing the susceptor and disposed to be spaced apart from the susceptor; and a blocking structure disposed between plates, among the plurality of plates, disposed adjacent to each other, wherein a distance between the showerhead structure and the susceptor is less than a distance between the plurality of plates and the susceptor, and a distance between the blocking structure and the susceptor is less than the distance between the plurality of plates and the susceptor.

公开(公告)号：US09263588B2

公开(公告)日：2016-02-16

申请号：US14635034

申请日：2015-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

公开(公告)号：US09847422B2

公开(公告)日：2017-12-19

申请号：US15290269

申请日：2016-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L21/308

CPC classification number: H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

公开(公告)号：US08969939B2

公开(公告)日：2015-03-03

申请号：US13960434

申请日：2013-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

IPC: H01L29/792 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/115 ,  H01L21/28 ,  H01L21/762 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Abstract translation: 半导体器件包括限定形成在半导体衬底中的有源区的隔离层。 在隔离层上执行第一凹陷处理以暴露活性区域的边缘部分。 执行第一舍入处理以围绕活动区域的边缘部分。 在隔离层上进行第二凹陷处理。 执行第二舍入处理以围绕活动区域的边缘部分。

公开(公告)号：US09905664B2

公开(公告)日：2018-02-27

申请号：US15604646

申请日：2017-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Namkoong ,  Dong-Kyum Kim ,  Jung-Hwan Kim ,  Jung Geun Jee ,  Han-Vit Yang ,  Ji-Man Yoo

IPC: H01L29/792 ,  H01L21/336 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11565 ,  H01L27/11582

CPC classification number: H01L29/42328 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/42324 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7926

Abstract: A semiconductor device includes a substrate, a tunnel insulation pattern on the substrate, a charge storage pattern on the tunnel insulation pattern, a dielectric pattern having a width smaller than a width of the charge storage pattern on the charge storage pattern, a control gate having a width greater than the width of the dielectric pattern on the dielectric pattern, and a metal-containing gate on the control gate.

公开(公告)号：US09595612B2

公开(公告)日：2017-03-14

申请号：US15006522

申请日：2016-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

IPC: H01L29/76 ,  H01L29/78 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Abstract translation: 半导体器件包括限定形成在半导体衬底中的有源区的隔离层。 在隔离层上执行第一凹陷处理以暴露活性区域的边缘部分。 执行第一舍入处理以围绕活动区域的边缘部分。 在隔离层上进行第二凹陷处理。 执行第二舍入处理以围绕活动区域的边缘部分。

公开(公告)号：US09184232B2

公开(公告)日：2015-11-10

申请号：US14538046

申请日：2014-11-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

IPC: H01L29/06 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

公开(公告)号：US20130320461A1

公开(公告)日：2013-12-05

申请号：US13960434

申请日：2013-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG-HWAN KIM ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

公开(公告)号：US09536896B2

公开(公告)日：2017-01-03

申请号：US14674583

申请日：2015-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Hoon Lee ,  Jin-Gyun Kim ,  Hyun Namkoong ,  Ki-Hyun Hwang ,  Hun-Hyeong Lim ,  Dong-Kyum Kim

IPC: H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L29/4234 ,  H01L29/7889 ,  H01L29/7926

Abstract: A non-volatile memory device having a vertical structure includes a semiconductor layer, a sidewall insulation layer extending in a vertical direction on the semiconductor layer, and having one or more protrusion regions, first control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of portions of the sidewall insulation layer where the one or more protrusion regions are not formed and second control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of the one or more protrusion regions.

Abstract translation: 具有垂直结构的非易失性存储器件包括半导体层，在半导体层上沿垂直方向延伸的侧壁绝缘层，并且具有一个或多个突出区域，在半导体层上沿垂直方向布置的第一控制栅电极 并且分别接触在半导体层上形成有一个或多个突起区域的侧壁绝缘层的一部分和在垂直方向上排列的第二控制栅电极，并分别接触一个或多个突出区域中的一个。

公开(公告)号：US20160155838A1

公开(公告)日：2016-06-02

申请号：US15006522

申请日：2016-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.