公开(公告)号：US20210005731A1

公开(公告)日：2021-01-07

申请号：US17028205

申请日：2020-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngtek OH ,  Jinwook JUNG ,  Hyeokshin KWON ,  Wontaek SEO ,  Insu JEON

IPC: H01L29/45 ,  H01L29/786 ,  H01L29/16

Abstract: A silicene electronic device includes a silicene material layer. The silicene material layer of the silicene electronic device has a 2D honeycomb structure of silicon atoms, is doped with at least one material of Group I, Group II, Group XVI, and Group XVII, and includes at least one of a p-type dopant region doped with a p-type dopant and an n-type dopant region doped with an n-type dopant. An electrode material layer including a material having a work function lower than the electron affinity of silicene is formed on the silicene material layer.

公开(公告)号：US20220149501A1

公开(公告)日：2022-05-12

申请号：US17515055

申请日：2021-10-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehyeong LEE ,  Hyeokshin KWON ,  Jaeho SHIN ,  Taehwan JANG ,  Insu JEON

IPC: H01P3/00 ,  H01P7/08 ,  G06N10/00

Abstract: A qubit memory of a quantum computer is provided. The qubit memory according to an embodiment includes a first readout unit, a first transmon, and a first data storage unit storing quantum information, and the first data storage unit includes a first superconducting waveguide layer, an insulating layer, and a superconductor layer sequentially stacked on a substrate. In one example, the first superconducting waveguide layer may include a superconducting resonator.

公开(公告)号：US20210216899A1

公开(公告)日：2021-07-15

申请号：US16916832

申请日：2020-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyeong LEE ,  Hyeokshin KWON ,  Insu JEON

IPC: G06N10/00 ,  H01L27/18

Abstract: Provided is a three-dimensional (3D) transmon qubit apparatus including a body portion, a driver, a transmon element disposed in an internal space of the body portion, a first tunable cavity module disposed in the internal space of the body, and comprising a first superconductive metal panel; and a second tunable cavity module disposed in the internal space of the body, and comprising a second superconductive metal panel, wherein the transmon element is disposed between the first superconductive metal panel and the second superconductive metal panel; wherein the first tunable cavity module and the second tunable cavity module are configured to adjust a distance between the first superconductive metal panel and the second superconductive metal panel, and wherein the driver is configured to tune a resonance frequency by adjusting a 3D cavity by adjusting the distance between the first superconductive metal panel and the second superconductive metal panel.

公开(公告)号：US20150214048A1

公开(公告)日：2015-07-30

申请号：US14309128

申请日：2014-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwansoo SUH ,  Insu JEON ,  Young Jae SONG ,  Qinke WU ,  Seong-jun JUNG

IPC: H01L21/02

CPC classification number: H01L21/02527 ,  H01L21/02425 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0262 ,  H01L21/02664

Abstract: According to example embodiments, a method of forming a multilayer graphene structure includes forming a sacrificial layer on the growth substrate, growing a first graphene layer on the sacrificial layer using a chemical vapor deposition (CVD) method, and growing at least one more graphene layer on the growth substrate. The growing at least one more graphene layer includes removing at least a part of the sacrificial layer.

Abstract translation: 根据示例性实施例，形成多层石墨烯结构的方法包括在生长衬底上形成牺牲层，使用化学气相沉积（CVD）方法在牺牲层上生长第一石墨烯层，并且生长至少一个以上石墨烯层 在生长底物上。 生长至少一个以上的石墨烯层包括去除牺牲层的至少一部分。

公开(公告)号：US20240260487A1

公开(公告)日：2024-08-01

申请号：US18488645

申请日：2023-10-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehyeong LEE ,  Jinhyoun KANG ,  Insu JEON ,  Jaeho SHIN

IPC: H10N69/00

CPC classification number: H10N69/00

Abstract: A qubit chip device includes: a substrate; a superconducting qubit on the substrate; and a readout circuit on the substrate and electrically connected to the superconducting qubit, the readout circuit including: a signal line on a surface of the substrate; a ground plate on the surface of the substrate, the ground plate including a pattern forming a coplanar waveguide along the signal line and offset from the signal line; and a conductive bridge embedded in the substrate and connecting two portions of the ground plate in a direction crossing the signal line.

公开(公告)号：US20210234016A1

公开(公告)日：2021-07-29

申请号：US17227456

申请日：2021-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngtek OH ,  Jinwook JUNG ,  Seunggeol NAM ,  Wontaek SEO ,  Insu JEON

IPC: H01L29/45

Abstract: Provided are transistors including an electride electrode. The transistor includes a substrate, a source region and a drain region doped with ions of different polarity from the substrate in a surface of the substrate, a source electrode and a drain electrode including an electride material on the source region and the drain region, a gate insulating layer surrounding the source electrode and a drain electrode on the substrate, and a gate electrode between the source electrode and the drain electrode on the substrate. The source electrode and the drain electrode have an ohmic contact with the substrate.

公开(公告)号：US20170186934A1

公开(公告)日：2017-06-29

申请号：US15388668

申请日：2016-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeokshin KWON ,  Youngtek OH ,  Insu JEON

IPC: H01L39/22 ,  G06N99/00

CPC classification number: H01L39/223 ,  G06N99/002 ,  H01L27/18

Abstract: Multi-qubit devices and quantum computers including the same are provided. The multi-qubit device may include a first layer including a plurality of qubits; a second layer that is disposed on the first layer, and comprises a plurality of flux generating elements that apply flux to the plurality of qubits, a plurality of wire patterns that provide current to the plurality of flux generating elements, and a plurality of plugs that are disposed perpendicular to the plurality of flux generating elements and the plurality of wire patterns and interconnect the plurality of flux generating elements and the plurality of wire patterns. Each of the plurality of flux generating elements may be integrated with a corresponding one of the plurality of wire patterns and a corresponding one of the plurality of plugs.

公开(公告)号：US20210328127A1

公开(公告)日：2021-10-21

申请号：US17227661

申请日：2021-04-12

Applicant: Samsung Electronics Co., Ltd

Inventor： Hyeokshin KWON ,  Jaehyeong LEE ,  Insu JEON

IPC: H01L39/22 ,  H01L39/02 ,  G06N10/00

Abstract: Provided is a quantum computing device and system. The quantum computing device includes a first qubit chip, a readout cavity structure surrounding a first end part of the first qubit chip, and a storage cavity structure surrounding a second end part of the first qubit chip, wherein the first qubit chip includes a first readout antenna disposed within the readout cavity structure, a first storage antenna disposed in the storage cavity structure, and a first qubit element provided between the first readout antenna and the first storage antenna, and wherein the first qubit element is disposed between the readout cavity structure and the storage cavity structure.

公开(公告)号：US20170077226A1

公开(公告)日：2017-03-16

申请号：US15261229

申请日：2016-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngtek OH ,  Hyeokshin KWON ,  Hwansoo SUH ,  Insu JEON

IPC: H01L29/06 ,  H01L29/861 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02425 ,  H01L21/02444 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02499 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02601 ,  H01L21/02603 ,  H01L21/02631 ,  H01L21/02639 ,  H01L29/16 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78 ,  H01L29/861

Abstract: Provided are methods of forming nanostructures, methods of manufacturing semiconductor devices using the same, and semiconductor devices including nanostructures. A method of forming a nanostructure may include forming an insulating layer and forming a nanostructure on the insulating layer. The insulating layer may have a crystal structure. The insulating layer may include an insulating two-dimensional (2D) material. The insulating 2D material may include a hexagonal boron nitride (h-BN). The insulating layer may be formed on a catalyst metal layer. The nanostructure may include at least one of silicon (Si), germanium (Ge), and SiGe. The nanostructure may include at least one nanowire.

Abstract translation: 提供形成纳米结构的方法，制造使用其的半导体器件的制造方法以及包括纳米结构的半导体器件。 形成纳米结构的方法可以包括在绝缘层上形成绝缘层并形成纳米结构。 绝缘层可以具有晶体结构。 绝缘层可以包括绝缘二维（2D）材料。 绝缘2D材料可以包括六方氮化硼（h-BN）。 绝缘层可以形成在催化剂金属层上。 纳米结构可以包括硅（Si），锗（Ge）和SiGe中的至少一种。 纳米结构可以包括至少一个纳米线。

公开(公告)号：US20160247942A1

公开(公告)日：2016-08-25

申请号：US15051270

申请日：2016-02-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Insu JEON ,  Jiyeon KU ,  Hyowon KIM

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/04 ,  H01L29/16

CPC classification number: H01L29/78696 ,  H01L21/02425 ,  H01L21/02488 ,  H01L21/02499 ,  H01L21/02527 ,  H01L21/02664 ,  H01L21/044 ,  H01L29/1606 ,  H01L29/66045

Abstract: A method includes growing a graphene layer on a metal layer, intercalating a first material between the metal layer and the graphene layer by heating the first material at a first pressure and a first temperature, and intercalating a second material between the metal layer and the graphene layer by heating the second material at a second pressure different from the first pressure and a second temperature different from the first temperature. Accordingly, the first material and the second material are chemically bonded to each other to form an insulating layer, and the insulating layer may be between the metal layer and the graphene layer.

Abstract translation: 一种方法包括在金属层上生长石墨烯层，通过在第一压力和第一温度下加热第一材料，在金属层和石墨烯层之间插入第一材料，并在金属层和石墨烯之间插入第二材料 在不同于第一压力的第二压力和不同于第一温度的第二温度下加热第二材料。 因此，第一材料和第二材料彼此化学键合以形成绝缘层，绝缘层可以在金属层和石墨烯层之间。