公开(公告)号：US11990439B2

公开(公告)日：2024-05-21

申请号：US17343992

申请日：2021-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeean Lee ,  Changeun Joo ,  Gyujin Choi

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/495 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065

CPC classification number: H01L24/14 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53204 ,  H01L2224/0401

Abstract: A semiconductor package including a semiconductor chip; a lower redistribution layer on a lower surface of the semiconductor chip; a lower passivation layer on a lower surface of the lower redistribution layer; a UBM pad on the lower passivation layer and including an upper pad and a lower pad connected to the upper pad, the upper pad having a greater horizontal length at an upper surface thereof than a horizontal length at a lower surface thereof; a seed layer between the lower passivation layer and the UBM pad; and an external connecting terminal on a lower surface of the UBM pad, wherein the seed layer includes a first seed part covering a side surface of the upper pad, a second seed part covering a portion of the lower surface of the upper pad, and a third seed part covering a portion of a side surface of the lower pad.

公开(公告)号：US20250062252A1

公开(公告)日：2025-02-20

申请号：US18742833

申请日：2024-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeean Lee ,  Dongwon Kang ,  Changyeon Song ,  Sunguk Lee

IPC: H01L23/58 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package includes a redistribution insulation layer and a connection structure disposed on the redistribution insulation layer in a first direction and including a base layer, a metal pattern, and a cavity. A semiconductor chip is disposed on the redistribution insulation layer in the first direction. The semiconductor chip is spaced apart from the connection structure by a molding layer. The semiconductor chip and the molding layer are disposed in the cavity. The metal pattern is disposed on the redistribution insulation layer, at least partially between the base layer and the molding layer. The metal pattern includes a first metal pattern extending, in a second direction crossing the first direction, from an inner surface of the connection structure into the base layer and separating at least a portion of the base layer from at least a portion of the redistribution insulation layer.

公开(公告)号：US20200185357A1

公开(公告)日：2020-06-11

申请号：US16685575

申请日：2019-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungsoo BYUN ,  Taesung Jeong ,  Younggwan Ko ,  Jaeean Lee

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes an interposer having multiple connection structures, each including redistribution layers electrically connected to each other, and a passivation layer covering at least a portion of each of the connection structures and filling a space between the connection structures. A first semiconductor chip is disposed on the interposer and has first connection pads, and a second semiconductor chip is disposed adjacent to the first semiconductor chip on the interposer and has second connection pads. The connection structures are independently arranged to each at least partially overlap with one or both of the first and second semiconductor chips, in a stacking direction of the first and second semiconductor chips on the interposer. The redistribution layers of each of the connection structures are electrically connected to at least one of the first and second connection pads via under bump metals.

公开(公告)号：US20250079382A1

公开(公告)日：2025-03-06

申请号：US18807488

申请日：2024-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeean Lee ,  Dongwon Kang ,  Dahee Kim ,  Changyeon Song ,  Sunguk Lee

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538

Abstract: Provided is a semiconductor package including a lower package substrate including lower insulating layers, a first semiconductor device mounted on the lower package substrate, a core layer on the lower package substrate to be laterally spaced apart from the first semiconductor device, an encapsulation material surrounding the first semiconductor device and covering an upper portion of the core layer, an upper package substrate disposed on the encapsulation material, the upper package substrate including a first upper redistribution layer and a second upper redistribution layer; wherein a first line width and a first line spacing of a first fine pattern of the first upper redistribution pattern are greater than or equal to a corresponding second line width and a corresponding second line spacing of a second fine pattern of the second upper redistribution pattern, respectively.

公开(公告)号：US12218099B2

公开(公告)日：2025-02-04

申请号：US17392511

申请日：2021-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungsoo Byun ,  Taesung Jeong ,  Younggwan Ko ,  Jaeean Lee

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package includes an interposer, first and second semiconductor chips, and electrical connection structures. The interposer includes a first connection structure having a first redistribution conductor, second connection structures each having a second redistribution conductor, third connection structures each having a third redistribution conductor, and a passivation layer filling spaces between the first to third connection structures. The first semiconductor chip is disposed on the interposer to overlap the first connection structure and some third connection structures. The second semiconductor chip is disposed on the interposer to overlap some second connection structures and third connection structures. The electrical connection structures are electrically connected to the first and second chips. The first redistribution conductor electrically connects the first chip to some electrical connection structures, the second redistribution conductor electrically connects the second chip to some electrical connection structures, and the third redistribution conductor electrically connects the first and second chips.

公开(公告)号：US20240347487A1

公开(公告)日：2024-10-17

申请号：US18368640

申请日：2023-09-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeean Lee ,  Dahee Kim ,  Taehoon Lee ,  Gyujin Choi

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/05 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/06 ,  H01L24/08 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/03462 ,  H01L2224/05548 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0601 ,  H01L2224/08225 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/73265 ,  H01L2924/1815

Abstract: An upper redistribution wiring layer of a semiconductor package includes a protective layer provided on at least one upper insulating layer and having an opening that exposes at least a portion of an uppermost redistribution wiring among second redistribution wirings, and a bonding pad provided on the uppermost redistribution wiring through the opening. The bonding pad includes a first plating pattern formed on the uppermost redistribution wiring, the first plating pattern including a via pattern provided in the opening and a pad pattern formed on the via pattern to be exposed from the opening, a second plating pattern on the second plating pattern, and a third plating pattern on the second plating pattern.

公开(公告)号：US20240063131A1

公开(公告)日：2024-02-22

申请号：US18203239

申请日：2023-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeean Lee ,  Dahee Kim ,  Taehoon Lee ,  Gyujin Choi

IPC: H01L23/538 ,  H10B80/00 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/5385 ,  H10B80/00 ,  H01L25/18 ,  H01L25/50 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/29 ,  H01L2224/19 ,  H01L2224/211 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29194 ,  H01L2924/0665 ,  H01L2224/32225 ,  H01L24/73 ,  H01L2224/73204 ,  H01L24/33 ,  H01L2224/33181 ,  H01L2224/73267 ,  H01L2224/32221 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/1441 ,  H01L2924/14335 ,  H01L23/3128

Abstract: A semiconductor package includes a first substrate having a first surface and a second surface, and having a cavity extending from the first surface to the second surface in a vertical direction, a first chip disposed in the cavity of the first substrate, a redistribution structure on the first surface of the first substrate, a second chip on the redistribution structure, a third chip spaced apart from the second chip in a horizontal direction and disposed on the redistribution structure, and a bridge chip embedded in the redistribution structure, wherein the redistribution structure includes a first redistribution pattern, a second redistribution pattern, and a third redistribution pattern.

公开(公告)号：US11417595B2

公开(公告)日：2022-08-16

申请号：US16991306

申请日：2020-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seunghun Chae ,  Youngkwan Seo ,  Jaeean Lee ,  Soyeon Moon ,  Hyeyeong Jo ,  Iljong Seo

IPC: H01L23/495 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces, and an insulating member and a plurality of redistribution layers on different levels in the insulating member and electrically connected together; a plurality of under bump metallurgy (UBM) pads in the insulating member and connected to a redistribution layer, among the plurality of redistribution layers, adjacent to the first surface, the UBM pads having a lower surface exposed to the first surface of the redistribution substrate; a dummy pattern between the UBM pads in the insulating member, the dummy pattern having a lower surface located at a level higher than the lower surface of the UBM pads; and at least one semiconductor chip on the second surface of the redistribution substrate and having a plurality of contact pads electrically connected to a redistribution layer, among the plurality of redistribution layers, adjacent to the second surface.

公开(公告)号：US11088115B2

公开(公告)日：2021-08-10

申请号：US16685575

申请日：2019-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungsoo Byun ,  Taesung Jeong ,  Younggwan Ko ,  Jaeean Lee

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes an interposer having multiple connection structures, each including redistribution layers electrically connected to each other, and a passivation layer covering at least a portion of each of the connection structures and filling a space between the connection structures. A first semiconductor chip is disposed on the interposer and has first connection pads, and a second semiconductor chip is disposed adjacent to the first semiconductor chip on the interposer and has second connection pads. The connection structures are independently arranged to each at least partially overlap with one or both of the first and second semiconductor chips, in a stacking direction of the first and second semiconductor chips on the interposer. The redistribution layers of each of the connection structures are electrically connected to at least one of the first and second connection pads via under bump metals.