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    ELECTRONIC DEVICE FOR PERFORMING DEVICE-TO-DEVICE COMMUNICATION AND METHOD THEREFOR
    1.
    发明申请
    ELECTRONIC DEVICE FOR PERFORMING DEVICE-TO-DEVICE COMMUNICATION AND METHOD THEREFOR 有权

    公开(公告)号：US20210045073A1

    公开(公告)日：2021-02-11

    申请号：US16979761

    申请日：2019-03-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yusung JOO ,  Jaejun LEE ,  Jaesung PARK ,  Wonshik YOON

    IPC: H04W56/00 ,  H04W76/14

    Abstract: According to various embodiments, an electronic device comprises a communication circuit, a processor, and a memory electrically connected to the processor, wherein the memory, when executed, can store commands for allowing the processor to: receive, from a first external electronic device, a first synchronization signal including first identification information through the communication circuit; synchronize the electronic device with the first external electronic device on the basis of at least a part of the information included in the first synchronization signal; receive, from a second external electronic device, a second synchronization signal including second identification information through the communication circuit; and control, on the basis of the second identification information and the first identification information, whether synchronization with second external electronic device occurs. Additional various embodiments are possible.

    APPARATUS, MEMORY DEVICE, AND METHOD FOR MULTI-PHASE CLOCK TRAINING
    3.
    发明公开
    APPARATUS, MEMORY DEVICE, AND METHOD FOR MULTI-PHASE CLOCK TRAINING 审中-公开

    公开(公告)号：US20230147016A1

    公开(公告)日：2023-05-11

    申请号：US17959663

    申请日：2022-10-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taegook KIM ,  Woojin NA ,  Taegeun YOO ,  Hyeseung YU ,  Jaejun LEE

    IPC: G11C7/22 ,  G11C7/10

    CPC classification number: G11C7/222 ,  G11C7/109 ,  G11C7/1072

    Abstract: Provided are an apparatus, a memory device, and a method for multi-phase clock training. The memory device includes a clock training circuit configured to receive a clock through a first signal pin, among a plurality of signal pins and connected to a first signal line connected to the first signal pin. The clock training circuit generates a multi-phase clock upon receiving the clock, and generates a three-dimensional (3-D) duty offset code (DOC) for the multi-phase clock by simultaneously phase-sweeping between three internal clock signals in a duty adjustment step in the multi-phase clock. The memory device corrects a duty error of the multi-phase clock using the 3-D DOC.

    MOTOR AND WASHING MACHINE HAVING THE SAME
    8.
    发明申请
    MOTOR AND WASHING MACHINE HAVING THE SAME 审中-公开

    公开(公告)号：US20200295645A1

    公开(公告)日：2020-09-17

    申请号：US16819286

    申请日：2020-03-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jinki LEE ,  Jaejun LEE ,  Minseong IM ,  Sukwon JEONG

    IPC: H02K29/03 ,  H02K1/27 ,  H02K21/22 ,  D06F37/30 ,  D06F23/04 ,  D06F37/40

    Abstract: A motor of the invention includes a stator having a slot wound with a coil and a circular shaped housing accommodating the stator, and a rotor disposed on an inner surface of the housing and spaced apart from the slot and having a plurality of permanent magnets having the same number as magnetic poles and having different magnetic polarities. Each of the plurality of permanent magnets has a length corresponding to a first angle according to the number of magnetic poles. The plurality of permanent magnets are spaced apart from each other at a third angle according to the first angle and a second angle corresponding to the number of magnetic poles. The first, second, third angles of the motor refer to a center point of the housing as an angle reference point. The motor of an embodiment may be a motor provided in a washing machine.

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