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    SEMICONDUCTOR LIGHT EMITTING DEVICE HAVING MULTI-CELL ARRAY AND METHOD OF MANUFACTURING THE SAME
    2.
    发明申请
    SEMICONDUCTOR LIGHT EMITTING DEVICE HAVING MULTI-CELL ARRAY AND METHOD OF MANUFACTURING THE SAME 有权
    具有多个细胞阵列的半导体发光器件及其制造方法

    公开(公告)号：US20140008665A1

    公开(公告)日：2014-01-09

    申请号：US13933887

    申请日：2013-07-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Su Hyun JO ,  Jong Ho LEE ,  Jin Hyun LEE ,  Chan Mook LIM ,  Jin Hwan KIM

    IPC: H01L27/15 ,  H01L33/00

    CPC classification number: H01L27/15 ,  H01L27/156 ,  H01L33/005 ,  H01L33/20 ,  H01L2933/0016

    Abstract: A method of manufacturing a semiconductor light emitting device having a multi-cell array, including: sequentially forming a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer on a substrate; etching and removing portions of the second conductive semiconductor layer and the active layer so as to expose portions of an upper surface of the first conductive semiconductor layer corresponding to respective regions of the second conductive semiconductor layer spaced apart from one another; and separating light emitting cells by partially etching the exposed portions of the first conductive semiconductor layer, wherein the separating of the light emitting cells is not performed at an edge portion of the substrate.

    Abstract translation: 一种制造具有多单元阵列的半导体发光器件的方法，包括：在衬底上依次形成第一导电半导体层，有源层和第二导电半导体层; 蚀刻和去除所述第二导电半导体层和所述有源层的部分，以便暴露所述第一导电半导体层的与所述第二导电半导体层彼此间隔开的相应区域的上表面的部分; 以及通过部分蚀刻所述第一导电半导体层的暴露部分来分离发光单元，其中在所述基板的边缘部分处不发生所述发光单元的分离。

    SEMICONDUCTOR PACKAGE
    3.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20220293565A1

    公开(公告)日：2022-09-15

    申请号：US17531115

    申请日：2021-11-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seung Hun SHIN ,  Un Byoung KANG ,  Yeong Kwon KO ,  Jong Ho LEE ,  Teak Hoon LEE ,  Jun Yeong HEO

    IPC: H01L25/065 ,  H01L23/48 ,  H01L23/498 ,  H01L23/31

    Abstract: There is provided a semiconductor device comprising a first semiconductor chip which includes a first chip substrate, and a first through via penetrating the first chip substrate, a second semiconductor chip disposed on the first semiconductor chip, and includes a second chip substrate, and a second through via penetrating the second chip substrate, and a connecting terminal disposed between the first semiconductor chip and the second semiconductor chip to electrically connect the first through via and the second through via. The semiconductor device further comprising an inter-chip molding material which includes a filling portion that fills between the first semiconductor chip and the second semiconductor chip and encloses the connecting terminal, an extension portion that extends along at least a part of a side surface of the second semiconductor chip, and a protruding portion protruding from the extension portion.

    SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20180212067A1

    公开(公告)日：2018-07-26

    申请号：US15933505

    申请日：2018-03-23

    Applicant: Samsung Electronics Co, Ltd

    Inventor： Jong Ho LEE ,  Ho Jun Kim ,  Sung Dae Suk ,  Geum Jong Bae

    IPC: H01L29/786 ,  H01L29/423 ,  H01L29/06

    Abstract: A semiconductor device according to example embodiments of inventive concepts may include a substrate, source/drain regions extending perpendicular to an upper surface of the substrate, a plurality of nanosheets on the substrate and separated from each other, and a gate electrode and a gate insulating layer on the substrate. The nanosheets define channel regions that extend in a first direction between the source/drain regions. The gate electrode surrounds the nanosheets and extends in a second direction intersecting the first direction. The gate insulating layer is between the nanosheets and the gate electrode. A length of the gate electrode in the first direction may be greater than a space between adjacent nanosheets among the nanosheets.

    SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20170345946A1

    公开(公告)日：2017-11-30

    申请号：US15666844

    申请日：2017-08-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong Ho LEE ,  Ho Jun KIM ,  Sung Dae SUK ,  Geum Jong BAE

    IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423

    CPC classification number: H01L29/78696 ,  H01L29/0665 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66545

    Abstract: A semiconductor device according to example embodiments of inventive concepts may include a substrate, source/drain regions extending perpendicular to an upper surface of the substrate, a plurality of nanosheets on the substrate and separated from each other, and a gate electrode and a gate insulating layer on the substrate. The nanosheets define channel regions that extend in a first direction between the source/drain regions. The gate electrode surrounds the nanosheets and extends in a second direction intersecting the first direction. The gate insulating layer is between the nanosheets and the gate electrode. A length of the gate electrode in the first direction may be greater than a space between adjacent nanosheets among the nanosheets.

    SEMICONDUCTOR PACKAGE
    6.
    发明公开
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20230253343A1

    公开(公告)日：2023-08-10

    申请号：US18301606

    申请日：2023-04-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jin-woo PARK ,  Un-Byoung KANG ,  Jong Ho LEE

    IPC: H01L23/00 ,  H01L23/498 ,  H01L23/14

    CPC classification number: H01L23/562 ,  H01L23/49816 ,  H01L24/14 ,  H01L23/14

    Abstract: A semiconductor package includes a first substrate including a circuit pattern and a dummy pattern on an upper face of the first substrate, a solder ball, a second substrate on the first substrate, and an underfill material layer between the first and second substrates. The underfill material layer wraps around the solder ball. The dummy pattern is not electrically connected to the circuit pattern. The first substrate includes a solder resist layer on the circuit pattern and the dummy pattern. The solder resist layer includes a first opening for exposing at least a part of the circuit pattern. The solder ball is in the first opening and electrically insulated from the dummy pattern by the solder resist layer. The second substrate is electrically connected to the first substrate by the solder ball. The second substrate is electrically insulated from the dummy pattern by the solder resist layer.

    MAGAZINE SUPPORTING EQUIPMENT AND SEMICONDUCTOR MANUFACTURING APPARATUS INCLUDING THE SAME
    7.
    发明申请
    MAGAZINE SUPPORTING EQUIPMENT AND SEMICONDUCTOR MANUFACTURING APPARATUS INCLUDING THE SAME 有权

    公开(公告)号：US20210391199A1

    公开(公告)日：2021-12-16

    申请号：US17200981

    申请日：2021-03-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jun Young OH ,  Seung Hwan KIM ,  Jong Ho PARK ,  Yong Kwan LEE ,  Jong Ho LEE

    IPC: H01L21/673

    Abstract: The present disclosure provides a magazine supporting equipment for supporting a magazine with multiple input ports. The magazine supporting equipment comprises a contact plate, a first sidewall plate, and a second sidewall plate. The contact plate is in contact with the magazine. The first sidewall plate extends vertically from one end of the contact plate. The second sidewall plate parallel is to the first sidewall plate and extends vertically from one end to the other end of the contact plate. The first sidewall plate extends along at least a part of a first sidewall of the magazine. The second sidewall plate extends along at least a part of a second sidewall of the magazine. The first sidewall plate and the second sidewall plate include control openings through which gas flows in and out.

    SEMICONDUCTOR LIGHT EMITTING DEVICE
    8.
    发明申请
    SEMICONDUCTOR LIGHT EMITTING DEVICE 有权
    半导体发光器件

    公开(公告)号：US20140219304A1

    公开(公告)日：2014-08-07

    申请号：US14154556

    申请日：2014-01-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jong Ho LEE ,  Chan Mook LIM ,  Young Chul SHIN ,  Su Hyun JO

    IPC: H01L33/62 ,  H01S5/02

    CPC classification number: H01S5/02 ,  H01L33/0079 ,  H01L33/382 ,  H01L33/44

    Abstract: A semiconductor light emitting device includes a conductive substrate, a light emitting laminate including a second conductivity type semiconductor layer, an active layer, and a first conductivity type semiconductor layer stacked on the conductive substrate, a first electrode layer electrically connected to the first conductivity type semiconductor layer, a second electrode layer between the conductive substrate and the second conductivity type semiconductor layer, the second electrode layer being electrically connected to the second conductivity type semiconductor layer, and a passivation layer between the active layer and the second electrode layer, the passivation layer covering at least a lateral surface of the active layer of the light emitting laminate.

    Abstract translation: 半导体发光器件包括导电衬底，层叠在导电衬底上的第二导电型半导体层，有源层和第一导电型半导体层的发光层叠体，与第一导电型电连接的第一电极层 半导体层，在导电基板和第二导电类型半导体层之间的第二电极层，第二电极层电连接到第二导电类型半导体层，以及在有源层和第二电极层之间的钝化层，钝化层 层覆盖发光层压板的有源层的至少一个侧表面。

    SEMICONDUCTOR PACKAGE
    9.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20240379626A1

    公开(公告)日：2024-11-14

    申请号：US18780917

    申请日：2024-07-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seung Hun SHIN ,  Un Byoung KANG ,  Yeong Kwon KO ,  Jong Ho LEE ,  Teak Hoon LEE ,  Jun Yeong HEO

    IPC: H01L25/065 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498

    Abstract: There is provided a semiconductor device comprising a first semiconductor chip which includes a first chip substrate, and a first through via penetrating the first chip substrate, a second semiconductor chip disposed on the first semiconductor chip, and includes a second chip substrate, and a second through via penetrating the second chip substrate, and a connecting terminal disposed between the first semiconductor chip and the second semiconductor chip to electrically connect the first through via and the second through via. The semiconductor device further comprising an inter-chip molding material which includes a filling portion that fills between the first semiconductor chip and the second semiconductor chip and encloses the connecting terminal, an extension portion that extends along at least a part of a side surface of the second semiconductor chip, and a protruding portion protruding from the extension portion.

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