公开(公告)号：US09640443B2

公开(公告)日：2017-05-02

申请号：US15154032

申请日：2016-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kug-Hwan Kim ,  Jong-Ho Lee ,  Woo-Hee Kim ,  Nae-In Lee

IPC: H01L21/321 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L27/092 ,  H01L27/11 ,  H01L29/66

CPC classification number: H01L21/823842 ,  H01L21/28202 ,  H01L21/823821 ,  H01L27/088 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/42364 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66545

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate including first through fourth areas. Moreover, first through fourth gate insulating layers are on the first through fourth areas, respectively. Amounts of work function control materials in the first through fourth gate insulating layers, nitrogen concentrations in the first through fourth gate insulating layers, and/or thicknesses of the first through fourth gate insulating layers vary among the first through fourth gate insulating layers. Methods for fabricating semiconductor devices are also provided.

公开(公告)号：US20160276225A1

公开(公告)日：2016-09-22

申请号：US15154032

申请日：2016-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kug-Hwan Kim ,  Jong-Ho Lee ,  Woo-Hee Kim ,  Nae-In Lee

IPC: H01L21/8238 ,  H01L27/11 ,  H01L29/66 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/28202 ,  H01L21/823821 ,  H01L27/088 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/42364 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66545

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate including first through fourth areas. Moreover, first through fourth gate insulating layers are on the first through fourth areas, respectively. Amounts of work function control materials in the first through fourth gate insulating layers, nitrogen concentrations in the first through fourth gate insulating layers, and/or thicknesses of the first through fourth gate insulating layers vary among the first through fourth gate insulating layers. Methods for fabricating semiconductor devices are also provided.

公开(公告)号：US20140363960A1

公开(公告)日：2014-12-11

申请号：US14271909

申请日：2014-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo-Hee Kim ,  Nae-In Lee ,  Kug-Hwan Kim ,  Jong-Ho Lee

IPC: H01L21/28

CPC classification number: H01L21/82345 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/823842 ,  H01L27/1104 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: Provided are methods for fabricating a semiconductor device. A gate dielectric layer is formed on a substrate including first through third regions. A first functional layer is formed on only the first region of the first through third regions. A second functional layer is formed on only the first and second regions of the first through third regions. A threshold voltage adjustment layer is formed on the first through third regions. The threshold voltage adjustment layer includes a work function adjustment material. The work function adjustment material is diffused into the gate dielectric layer by performing a heat treatment process with respect to the substrate.

Abstract translation: 提供了制造半导体器件的方法。 在包括第一至第三区域的衬底上形成栅极电介质层。 仅在第一至第三区域的第一区域上形成第一功能层。 仅在第一至第三区域的第一和第二区域上形成第二功能层。 在第一至第三区域上形成阈值电压调节层。 阈值电压调整层包括功函调整材料。 通过对基板进行热处理工艺，将功函调整材料扩散到栅介质层。

公开(公告)号：US09478551B2

公开(公告)日：2016-10-25

申请号：US14081543

申请日：2013-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Hun Kim ,  Ju-Youn Kim ,  Koung-Min Ryu ,  Jong-Mil Youn ,  Jong-Ho Lee

IPC: H01L21/70 ,  H01L29/76 ,  H01L27/11 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/1104 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/1029

Abstract: A semiconductor device includes a channel layer over an active region, first and second field regions adjacent the active region, and a gate structure over the channel layer and portions of the first and second field regions. The first and second field regions include grooves adjacent respective sidewalls of the channel layer, and bottom surfaces of the grooves are below a bottom surface of the channel layer.

Abstract translation: 半导体器件包括在有源区上的沟道层，与有源区相邻的第一和第二场区以及沟道层上的栅极结构以及第一和第二场区的部分。 第一和第二场区域包括与沟道层的相应侧壁相邻的沟槽，并且沟槽的底表面在沟道层的底表面下方。

公开(公告)号：US20130176803A1

公开(公告)日：2013-07-11

申请号：US13661773

申请日：2012-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Ho Lee ,  Kyu-Chang Kang ,  Hyo-Chang Kim ,  Jae-Youn Youn ,  Sang-Jae Rhee

IPC: G11C11/402 ,  G11C7/12 ,  G11C7/06

CPC classification number: G11C7/08 ,  G11C11/40626 ,  G11C11/4091 ,  G11C2211/4065 ,  G11C2211/4068

Abstract: A semiconductor memory device and a self-refresh method of the semiconductor memory device. The semiconductor memory device includes: a memory cell array including one or more memory cells; a sense amplifier connected to a sensing line and a complementary sensing line and sensing/amplifying data stored in the one or more memory cells; and a sense amplifier control circuit sequentially supplying a first voltage and a second voltage having different levels to the sense amplifier through the sensing line during a refresh operation.

Abstract translation: 半导体存储器件和半导体存储器件的自刷新方法。 半导体存储器件包括：包括一个或多个存储单元的存储单元阵列; 连接到感测线和互补感测线的感测放大器，以及感测/放大存储在所述一个或多个存储器单元中的数据; 以及读出放大器控制电路，其在刷新操作期间通过感测线路顺序地将具有不同电平的第一电压和第二电压提供给读出放大器。

公开(公告)号：US10056454B2

公开(公告)日：2018-08-21

申请号：US15336111

申请日：2016-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Jun Kim ,  Jong-Ho Lee ,  Geum-Jong Bae ,  Dong-Chan Suh

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/16 ,  H01L21/8234 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0665 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor device includes a semiconductor substrate. A first fin extends in a first direction. A first nano sheet structure includes at least two first nano sheets which extend in the first direction parallel to an upper surface of the first fin. A second fin extends in the first direction. A second nano sheet structure includes at least two second nano sheets which extend in the first direction parallel to an upper surface of the second fin. At least one of the at least two first nano sheets has a different thickness from at least one of the at least two second nano sheets.

公开(公告)号：US10115448B2

公开(公告)日：2018-10-30

申请号：US15194784

申请日：2016-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Ho Lee ,  Seung-Jun Shin ,  Tae-Young Oh

IPC: G11C11/406 ,  G06F3/06

Abstract: A memory device includes a memory bank including a plurality of memory blocks, a row selection circuit and a refresh controller. The row selection circuit is configured to perform an access operation and a refresh operation with respect to the memory bank. The refresh controller is configured to control the row selection circuit such that the memory device is operated selectively in an access mode or a self-refresh mode in response to a self-refresh command received from a memory controller, the refresh operation is performed in the access mode in response to an active command received from the memory controller and the refresh operation is performed in the self-refresh mode in response to at least one clock signal.

公开(公告)号：US09177865B2

公开(公告)日：2015-11-03

申请号：US14271909

申请日：2014-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo-Hee Kim ,  Nae-In Lee ,  Kug-Hwan Kim ,  Jong-Ho Lee

IPC: H01L27/11 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L21/82345 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/823842 ,  H01L27/1104 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: Provided are methods for fabricating a semiconductor device. A gate dielectric layer is formed on a substrate including first through third regions. A first functional layer is formed on only the first region of the first through third regions. A second functional layer is formed on only the first and second regions of the first through third regions. A threshold voltage adjustment layer is formed on the first through third regions. The threshold voltage adjustment layer includes a work function adjustment material. The work function adjustment material is diffused into the gate dielectric layer by performing a heat treatment process with respect to the substrate.

Abstract translation: 提供了制造半导体器件的方法。 在包括第一至第三区域的衬底上形成栅极电介质层。 仅在第一至第三区域的第一区域上形成第一功能层。 仅在第一至第三区域的第一和第二区域上形成第二功能层。 在第一至第三区域上形成阈值电压调节层。 阈值电压调整层包括功函调整材料。 通过对基板进行热处理工艺，将功函调整材料扩散到栅介质层。

公开(公告)号：US09105694B2

公开(公告)日：2015-08-11

申请号：US14286170

申请日：2014-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Ho Lee ,  Min-Keun Kwak ,  Bum-Joon Youn ,  Sung-Won Choi

IPC: H01L21/44 ,  H01L21/768 ,  H01L29/423 ,  H01L21/8234 ,  H01L27/108 ,  H01L29/66

CPC classification number: H01L21/76843 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/823842 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66545

Abstract: A method for making a semiconductor device includes forming a trench in a first layer on a substrate. A conductive layer having a pattern is formed in the trench. A first metal gate electrode is formed on the conductive layer, and a second metal gate electrode is formed on the first metal gate electrode. The first and second metal gate electrodes at least partially conform to the pattern of the conductive layer. Widths of first surfaces of the first and second metal gate electrodes are different from respective widths of second surfaces of the first and second metal gate electrodes as a result of the pattern.

Abstract translation: 制造半导体器件的方法包括在衬底上的第一层中形成沟槽。 在沟槽中形成具有图案的导电层。 第一金属栅电极形成在导电层上，第二金属栅电极形成在第一金属栅电极上。 第一和第二金属栅电极至少部分地符合导电层的图案。 作为图案的结果，第一和第二金属栅电极的第一表面的宽度不同于第一和第二金属栅电极的第二表面的宽度。