公开(公告)号：US11368829B2

公开(公告)日：2022-06-21

申请号：US16702065

申请日：2019-12-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Young Choi ,  Dong Yun Kim ,  Ivan Galkin ,  Ji-Hoon Park ,  Jong-Jin Lee

IPC: H04W4/70 ,  H04W4/80 ,  H04L67/125 ,  H04W76/28 ,  G06F9/445

Abstract: An electronic device includes a narrowband internet of things (NB-IoT) circuit; a shared central processor to control the narrowband internet of things circuit; a shared memory to store data or code from the shared central processor; and a communicator controlled by the shared central processor. The communicator stores the data or the code in the shared memory.

公开(公告)号：US10734309B2

公开(公告)日：2020-08-04

申请号：US16282682

申请日：2019-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Nam Kim ,  Tsukasa Matsuda ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Nae-In Lee ,  Jong-Jin Lee

IPC: H01L23/48 ,  H01L23/485 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a first trench, on a substrate a first liner layer formed along a side wall and a bottom surface of the first trench and including noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of International Union of Pure and Applied Chemistry (IUPAC) and belonging to one of eighth to tenth groups of the periodic chart, and a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom surface of the first trench.

公开(公告)号：US10332791B2

公开(公告)日：2019-06-25

申请号：US15805865

申请日：2017-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Yun Jeon ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Kyoung-Hee Nam ,  Jong-Jin Lee ,  Jae-Won Hwang

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/288 ,  H01L23/528 ,  H01L23/522 ,  H01L21/285

Abstract: A semiconductor device includes an insulating interlayer disposed on a substrate, a first protection pattern, a first barrier pattern, a first adhesion pattern, and a first conductive pattern. The insulating interlayer includes a via hole and a first trench. The via hole extends through a lower portion of the insulating interlayer. The first trench is connected to the via hole and extends through an upper portion of the insulating interlayer. The first protection pattern covers a lower surface and sidewalls of the via hole and a portion of a lower surface and a lower sidewall of the first trench, and includes a conductive material. The first barrier pattern covers the protection pattern and an upper sidewall of the first trench. The first adhesion pattern covers the first barrier pattern. The first conductive pattern is disposed on the first adhesion pattern, and fills the via hale and the first trench.

公开(公告)号：US09773699B2

公开(公告)日：2017-09-26

申请号：US15000302

申请日：2016-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Jin Lee ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jin-Nam Kim ,  Tsukasa Matsuda ,  Wan-Soo Park ,  Nae-In Lee ,  Jae-Won Chang ,  Eun-Ji Jung ,  Jeong-Ok Cha ,  Jae-Won Hwang ,  Jung-Ha Hwang

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76882 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238

Abstract: In a method of forming a wiring structure, a lower structure is formed on a substrate. An insulating interlayer is formed on the lower structure. The insulating interlayer is partially removed to form at least one via hole and a dummy via hole. An upper portion of the insulating interlayer is partially removed to form a trench connecting the via hole and the dummy via hole. A first metal layer filling the via hole and the dummy via hole is formed. A second metal layer filling the trench is formed on the first metal layer.

公开(公告)号：US20190189744A1

公开(公告)日：2019-06-20

申请号：US16274350

申请日：2019-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Nam Kim ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jong-Min Baek ,  Sang-Hoon Ahn ,  Nae-In Lee ,  Jong-Jin Lee ,  Ho-Yun Jeon ,  Eun-Ji Jung

IPC: H01L29/08 ,  H01L23/532 ,  H01L27/12 ,  H01L27/088 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L29/0847 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76852 ,  H01L21/76862 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/0886 ,  H01L27/1211

Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

公开(公告)号：US10217820B2

公开(公告)日：2019-02-26

申请号：US15632884

申请日：2017-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Nam Kim ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jong-Min Baek ,  Sang-Hoon Ahn ,  Nae-In Lee ,  Jong-Jin Lee ,  Ho-Yun Jeon ,  Eun-Ji Jung

IPC: H01L29/08 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L27/12

Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

公开(公告)号：US08738989B2

公开(公告)日：2014-05-27

申请号：US13859976

申请日：2013-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwan-Ho Kim ,  Jong-In Kim ,  Young-Wook Jang ,  Hee-Dong Shin ,  Bong-Chun Kang ,  Jong-Jin Lee

IPC: H03M13/00

CPC classification number: G06F11/10 ,  G06F11/1008 ,  H03M13/37 ,  H03M13/3707

Abstract: A method and apparatus for detecting a free page of a memory device, and a method and apparatus for decoding an error correction code by using the method and apparatus for detecting a free page are provided. Free page data read from the memory is converted into a converted codeword for inclusion as an element of an error correction code field. The converted codeword is compared to an initially set target codeword to detect an amount of non-identical bits. A page read from the memory is determined to be a free page when the amount of non-identical bits is equal to or less than an initially set threshold value.

Abstract translation: 提供一种用于检测存储装置的自由页面的方法和装置，以及通过使用用于检测空闲页面的方法和装置来解码纠错码的方法和装置。 从存储器读取的自由页面数据被转换为转换的码字，以作为纠错码字段的元素。 将转换的码字与初始设置的目标码字进行比较，以检测不相同比特的量。 当不相同比特量等于或小于初始设置的阈值时，从存储器读取的页面被确定为空闲页面。

公开(公告)号：US09728604B2

公开(公告)日：2017-08-08

申请号：US15059438

申请日：2016-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Nam Kim ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jong-Min Baek ,  Sang-Hoon Ahn ,  Nae-In Lee ,  Jong-Jin Lee ,  Ho-Yun Jeon ,  Eun-Ji Jung

IPC: H01L29/08 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L27/12

CPC classification number: H01L29/0847 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76852 ,  H01L21/76862 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/0886 ,  H01L27/1211

Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

公开(公告)号：US20150082000A1

公开(公告)日：2015-03-19

申请号：US14462774

申请日：2014-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min Hong ,  Sim Ji Lee ,  JaeYoung Hur ,  JiWoong Kwon ,  Il Park ,  Jong-Jin Lee ,  Jinyong Jung

IPC: G06F12/10 ,  G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/507 ,  G06F2212/6022 ,  G06F2212/654 ,  G06F2212/68 ,  G06F2212/681

Abstract: A memory management unit comprises an address translation unit that receives a memory access request as a virtual address and translates the virtual address to a physical address. A translation lookaside buffer stores page descriptors of a plurality of physical addresses, the address translation unit determining whether a page descriptor of a received virtual address is present in the translation lookaside buffer. A prefetch buffer stores page descriptors of the plurality of physical addresses. The address translation unit, in the event the page descriptor of the received virtual address is not present in the translation lookaside buffer, further determines whether the page descriptor of the received virtual address is present in the prefetch buffer; updates the translation lookaside buffer with the page descriptor in response to the determination; and performs a translation of the virtual address to a physical address using the page descriptor.

Abstract translation: 存储器管理单元包括地址转换单元，其接收作为虚拟地址的存储器访问请求并将虚拟地址转换为物理地址。 翻译后备缓冲器存储多个物理地址的页面描述符，地址转换单元确定所接收的虚拟地址的页面描述符是否存在于翻译后备缓冲器中。 预取缓冲器存储多个物理地址的页面描述符。 地址转换单元，在接收到的虚拟地址的页面描述符不存在于翻译后备缓冲器中的情况下，进一步确定接收的虚拟地址的页面描述符是否存在于预取缓冲器中; 响应于确定，用页面描述符更新翻译后备缓冲器; 并使用页面描述符执行虚拟地址到物理地址的转换。

公开(公告)号：US11985580B2

公开(公告)日：2024-05-14

申请号：US18214677

申请日：2023-06-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Young Choi ,  Dong Yun Kim ,  Ivan Galkin ,  Ji-Hoon Park ,  Jong-Jin Lee

IPC: H04W4/70 ,  G06F9/445 ,  H04L67/125 ,  H04W4/80 ,  H04W76/28

CPC classification number: H04W4/70 ,  G06F9/44573 ,  H04L67/125 ,  H04W4/80 ,  H04W76/28

Abstract: An electronic device includes a narrowband internet of things (NB-IoT) circuit; a shared central processor to control the narrowband internet of things circuit; a shared memory to store data or code from the shared central processor; and a communicator controlled by the shared central processor. The communicator stores the data or the code in the shared memory.