Abstract:
The present disclosure relates to semiconductor device fabricating methods. An example semiconductor device fabricating method comprises forming a substrate including a chip area and an outside chip area and having a first surface and a second surface opposite to the first surface, forming a first trench, having a first width on the first surface, in the outside chip area of the substrate, forming a second trench, having a second width smaller than the first width, within the first trench, forming a first overlay key filling the first trench and the second trench, forming an active pattern on the first surface of the substrate, forming a source/drain pattern and a gate electrode on the active pattern in the chip area, and forming a backside contact on the second surface using a bottom surface of the first overlay key in the second trench.
Abstract:
A semiconductor device including a first fin protruding on a substrate and extending in a first direction; a first gate electrode on the first fin, the first gate electrode intersecting the first fin; a first trench formed within the first fin at a side of the first gate electrode; a first epitaxial layer filling a portion of the first trench, wherein a thickness of the first epitaxial layer becomes thinner closer to a sidewall of the first trench; and a second epitaxial layer filling the first trench on the first epitaxial layer, wherein a boron concentration of the second epitaxial layer is greater than a boron concentration of the first epitaxial layer.
Abstract:
A method for manufacturing a semiconductor device includes performing a first ion implantation process on a substrate to form a lower dopant region in the substrate, patterning the substrate having the lower dopant region to form active patterns, and performing a second ion implantation process on the active patterns to form an upper dopant region in an upper portion of each of the active patterns. The lower and upper dopant regions have a same conductivity type.
Abstract:
Semiconductor devices are provided. The semiconductor devices include active fins including a buffer layer disposed on a substrate and a channel layer disposed on the buffer layer and having a first second lattice constant higher than a lattice constant of the buffer layer, a gate structure covering the channel layer and intersecting the active fins, sidewall spacers disposed on both sidewalls of the gate structure, and capping layers disposed to contact lower surfaces of the sidewall spacers and having a width substantially the same as a width of the lower surfaces of the sidewall spacers.
Abstract:
A semiconductor device includes a substrate including a logic cell region including active patterns spaced apart in a first direction and extending in a second direction different from the first direction, and an overlay key region including a back-side key pattern and a front-side key pattern, source/drain patterns on the active patterns of the logic cell region and spaced apart in the second direction, a channel pattern between the source/drain patterns, and a gate pattern extending in the first direction, crossing between the source/drain patterns, and surrounding at least a part of the channel pattern, wherein the substrate has an upper surface and a lower surface facing each other in a third direction different from the first direction and the second direction, and the back-side key pattern of the overlay key region extends into the lower surface of the substrate.
Abstract:
A method for manufacturing a semiconductor device includes performing a first ion implantation process on a substrate to form a lower dopant region in the substrate, patterning the substrate having the lower dopant region to form active patterns, and performing a second ion implantation process on the active patterns to form an upper dopant region in an upper portion of each of the active patterns. The lower and upper dopant regions have a same conductivity type.
Abstract:
A semiconductor device includes a substrate having first and second regions, first fin groups spaced along a first direction on the first region, each of the first fin groups including adjacent first and second fins having longitudinal directions in a second direction intersecting the first direction, and third to fifth fins spaced along a third direction on the second region, the third to fifth fins having longitudinal directions in a fourth direction intersecting the third direction. The third through fifth fins are at a first pitch, the first and second fins are at a second pitch equal to or smaller than the first pitch, each of the first fin groups is at a first group pitch greater than three times the first pitch and smaller than four times the first pitch, and a width of the first and second fins is same as width of the third fin.
Abstract:
A method for manufacturing a semiconductor device includes performing a first ion implantation process on a substrate to form a lower dopant region in the substrate, patterning the substrate having the lower dopant region to form active patterns, and performing a second ion implantation process on the active patterns to form an upper dopant region in an upper portion of each of the active patterns. The lower and upper dopant regions have a same conductivity type.
Abstract:
A semiconductor device including a first fin protruding on a substrate and extending in a first direction; a first gate electrode on the first fin, the first gate electrode intersecting the first fin; a first trench formed within the first fin at a side of the first gate electrode; a first epitaxial layer filling a portion of the first trench, wherein a thickness of the first epitaxial layer becomes thinner closer to a sidewall of the first trench; and a second epitaxial layer filling the first trench on the first epitaxial layer, wherein a boron concentration of the second epitaxial layer is greater than a boron concentration of the first epitaxial layer.
Abstract:
A semiconductor device includes a substrate having first and second regions, first fin groups spaced along a first direction on the first region, each of the first fin groups including adjacent first and second fins having longitudinal directions in a second direction intersecting the first direction, and third to fifth fins spaced along a third direction on the second region, the third to fifth fins having longitudinal directions in a fourth direction intersecting the third direction. The third through fifth fins are at a first pitch, the first and second fins are at a second pitch equal to or smaller than the first pitch, each of the first fin groups is at a first group pitch greater than three times the first pitch and smaller than four times the first pitch, and a width of the first and second fins is same as width of the third fin.