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    MEMORY CONTROLLER OPERATING METHOD OF MEMORY CONTROLLER AND MEMORY SYSTEM
    3.
    发明申请
    MEMORY CONTROLLER OPERATING METHOD OF MEMORY CONTROLLER AND MEMORY SYSTEM 有权

    公开(公告)号：US20210265005A1

    公开(公告)日：2021-08-26

    申请号：US17317506

    申请日：2021-05-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： MINUK KIM ,  BOHWAN JUN ,  HONG RAK SON ,  DONG-MIN SHIN ,  KIJUN LEE

    IPC: G11C29/42 ,  G06F11/10 ,  G06F3/06

    Abstract: An operating method of a memory controller that individually controls a plurality of memory units includes reading respective segments from the plurality of memory units based on a plurality of control signals; generating an output codeword based on the segments; performing error correction decoding on the output codeword; when a result of the error correction decoding indicates success, updating at least one of a plurality of accumulated error pattern information respectively corresponding to the plurality of memory units based on the result of the error correction decoding; and when the result of the error correction decoding indicates failure, regulating at least one of the plurality of control signals based on at least one of the plurality of accumulated error pattern information.

    MEMORY CONTROLLER, OPERATING METHOD OF MEMORY CONTROLLER AND MEMORY SYSTEM
    5.
    发明申请
    MEMORY CONTROLLER, OPERATING METHOD OF MEMORY CONTROLLER AND MEMORY SYSTEM 审中-公开

    公开(公告)号：US20200050513A1

    公开(公告)日：2020-02-13

    申请号：US16357431

    申请日：2019-03-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： MINUK KIM ,  BOHWAN JUN ,  HONG RAK SON ,  DONG-MIN SHIN ,  KIJUN LEE

    IPC: G06F11/10 ,  G06F3/06

    Abstract: An operating method of a memory controller that individually controls a plurality of memory units includes reading respective segments from the plurality of memory units based on a plurality of control signals; generating an output codeword based on the segments; performing error correction decoding on the output codeword; when a result of the error correction decoding indicates success, updating at least one of a plurality of accumulated error pattern information respectively corresponding to the plurality of memory units based on the result of the error correction decoding; and when the result of the error correction decoding indicates failure, regulating at least one of the plurality of control signals based on at least one of the plurality of accumulated error pattern information.

    SEMICONDUCTOR MEMORY DEVICES
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20240370335A1

    公开(公告)日：2024-11-07

    申请号：US18778475

    申请日：2024-07-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungrae Kim ,  KIJUN LEE ,  MYUNGKYU LEE ,  YEONGGEOL SONG ,  Jinhoon Jang ,  SUNGHYE CHO ,  Isak Hwang

    IPC: G06F11/10

    Abstract: A semiconductor memory device includes a memory cell array, a link error correction code (ECC) engine and on-die ECC engine. The memory cell array includes a plurality of volatile memory cells. The link ECC engine provides a main data by performing a first ECC decoding on a first coedword including the main data and a first parity data, and generates a first error flag based on a result of the first ECC decoding. The on-die ECC engine generates a second parity data by performing a first ECC encoding on the main data, provides a target page of the memory cell array with a second codeword including the main data and the second parity data in response to the first error flag being deactivated or generates a third codeword by changing at least one of bits of the second codeword in response to the first error flag being deactivated.

    MEMORY DEVICE, SYSTEM INCLUDING THE SAME, AND OPERATING METHOD OF MEMORY DEVICE
    8.
    发明公开
    MEMORY DEVICE, SYSTEM INCLUDING THE SAME, AND OPERATING METHOD OF MEMORY DEVICE 审中-公开

    公开(公告)号：US20240248850A1

    公开(公告)日：2024-07-25

    申请号：US18416558

    申请日：2024-01-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： DAEHYUN KIM ,  SEONGMUK KANG ,  JIHO KIM ,  KYOMIN SOHN ,  YEONGGEOL SONG ,  KIJUN LEE ,  MYUNGKYU LEE ,  SUKHAN LEE

    IPC: G06F12/0891 ,  G06F12/126

    CPC classification number: G06F12/0891 ,  G06F12/126

    Abstract: A memory system includes a system controller and a memory device. The system controller includes a memory controller configured to transmit a received address to a decoding module, and output, to the host device, decoded data. The decoding module includes a cache device and a decoder. The decoding module is configured to receive the data corresponding to the address from the memory device. The decoding module is configured transmit the data stored in the cache device to the memory controller in response to determining that the data corresponding to the address is stored in the cache device. The decoding module is configured to decode the data corresponding to the address to generate decoded data and store the decoded result in the cache device in response to determining that the data corresponding to the address is not stored in the cache device.

    MEMORY DEVICE AND REFRESH METHOD THEREOF
    9.
    发明公开
    MEMORY DEVICE AND REFRESH METHOD THEREOF 审中-公开

    公开(公告)号：US20230420027A1

    公开(公告)日：2023-12-28

    申请号：US18197084

    申请日：2023-05-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： EUN AE LEE ,  SUNGHYE CHO ,  KIJUN LEE ,  KYOMIN SOHN ,  MYUNGKYU LEE

    IPC: G11C11/406

    CPC classification number: G11C11/40622 ,  G11C11/40615

    Abstract: A memory device may include counters respectively corresponding to rows and each configured to count a number of accesses to a corresponding row, a refresh control circuit, a queue, and first flags respectively corresponding to the rows. The refresh control circuit may change a second flag set in a refresh period every refresh period, and determine whether to put an incoming row address into the queue based on a count value of a counter corresponding to a target row indicated by the incoming row address among the counters, a first flag value of a first flag corresponding to the target row among the first flags, and a second flag value of the second flag set in a current refresh period.

    MEMORY DEVICE AND METHOD READING DATA
    10.
    发明申请
    MEMORY DEVICE AND METHOD READING DATA 有权

    公开(公告)号：US20210334033A1

    公开(公告)日：2021-10-28

    申请号：US17090726

    申请日：2020-11-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： SUNGHYE CHO ,  KIJUN LEE ,  SUNG-RAE KIM ,  CHANKI KIM ,  YEONGGEOL SONG ,  YESIN RYU ,  JAEYOUN YOUN ,  MYUNGKYU LEE

    IPC: G06F3/06

    Abstract: A method for reading data from a memory includes; reading a codeword from the memory cells, correcting the errors when a number of errors in the codeword is less than a maximum number of correctable errors, correcting the errors when the number of errors in the codeword is equal to the maximum number of correctable errors and the errors correspond to a same sub-word line, and outputting signal indicating that the errors are an uncorrectable error when the number of errors of the codeword is equal to the maximum number of correctable errors and the errors correspond to different sub-word lines.

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