公开(公告)号：US20190279725A1

公开(公告)日：2019-09-12

申请号：US16423505

申请日：2019-05-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-SEOP SHIM ,  JAEHONG KIM

IPC: G11C16/26 ,  G11C16/34 ,  G06F11/10

Abstract: A storage device includes a nonvolatile memory device and a controller. A nonvolatile memory device includes a plurality of memory blocks. Each of the plurality of memory blocks is divided into a plurality of zones and is formed on a substrate. Each of the plurality of zones comprises one or more word lines. A controller performs a reliability verification read operation on a first zone of the plurality of zones of a memory block selected from the plurality of memory blocks if a number of read operations performed on the first zone reaches a first threshold value and performs the reliability verification read operation on a second zone of the plurality of zones of the selected memory block if a number of read operations performed on the second zone reaches a second threshold value.

公开(公告)号：US20180191977A1

公开(公告)日：2018-07-05

申请号：US15910532

申请日：2018-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YUNHWAN JUNG ,  SUNYOOL KANG ,  JAEHONG KIM

IPC: H04N5/369 ,  H04N5/3745 ,  H04N5/357

CPC classification number: H04N5/3698 ,  H04N5/3575 ,  H04N5/3745 ,  H04N5/3765 ,  H04N5/378

Abstract: A comparing circuit may include a first amplifier and a second amplifier. The first amplifier performs a correlated double sampling operation in response to a pixel signal and a ramp signal, and the second amplifier amplifies an output signal of the first amplifier. The second amplifier includes a current stabilization circuit that supplies current to the second amplifier during the correlated double sampling operation irrespective of the output signal of the first amplifier.

公开(公告)号：US20170287748A1

公开(公告)日：2017-10-05

申请号：US15624066

申请日：2017-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YISUNG HWANG ,  JUNGCHUL LEE ,  JAEHONG KIM ,  TAEGYEONG CHUNG

IPC: H01L21/67

CPC classification number: H01L21/67144 ,  H01L2924/0002 ,  Y10T156/1744 ,  Y10T156/1746 ,  Y10T156/1761 ,  Y10T156/1776 ,  H01L2924/00

Abstract: An apparatus for bonding semiconductor chips may comprise transfer rails configured to transfer substrates, loading members configured to load the substrates onto the transfer rails, unloading members configured to unload the substrates from the transfer rails, a first wafer supply unit configured to supply a first wafer including semiconductor chips, and/or a bonding unit configured to bond the semiconductor chips to the substrates. An apparatus for bonding semiconductor chips may comprise a transfer rail configured to transfer substrates, loading members configured to load the substrates onto the transfer rail, unloading members configured to unload the substrates from the transfer rail, a buffer member at a side of the transfer rail configured to temporarily receive the substrates loaded by the loading members, a first wafer supply unit configured to supply a first wafer including semiconductor chips, and/or a bonding unit configured to bond the semiconductor chips to the substrates.

公开(公告)号：US20170330860A1

公开(公告)日：2017-11-16

申请号：US15443963

申请日：2017-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-seop SHIM ,  JAEHONG KIM

IPC: H01L25/065 ,  G11C16/08 ,  G11C16/10 ,  H01L23/498 ,  H01L23/528 ,  G11C16/04 ,  G11C16/30 ,  H01L23/00

CPC classification number: H01L25/0657 ,  G11C5/04 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/30 ,  G11C29/021 ,  H01L23/49838 ,  H01L23/528 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2924/1438 ,  H01L2924/15311

Abstract: Disclosed is a data storage device including a controller and a multi-stack chip package, and a method of operating a data storage device. The multi-stack chip package includes a first semiconductor chip arranged on a package substrate, a second semiconductor chip arranged on the first semiconductor chip, and a third semiconductor chip is arranged between the first and second semiconductor chips. The controller can control the first to third semiconductor chips by using a feature parameter measured from each semiconductor chip and a target value that may be originally designed by a memory vendor.

公开(公告)号：US20140372714A1

公开(公告)日：2014-12-18

申请号：US14472072

申请日：2014-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KIJUN LEE ,  JAEHONG KIM ,  SEJIN LIM ,  JUNGSOO CHUNG

IPC: G06F12/06 ,  G06F11/10

CPC classification number: G06F12/06 ,  G06F7/58 ,  G06F7/584 ,  G06F7/724 ,  G06F11/1008 ,  G06F11/1012 ,  G06F11/1044 ,  G06F11/1048 ,  G06F12/0246 ,  G06F2212/251 ,  G11C7/1006 ,  G11C16/00 ,  H03M13/03

Abstract: A random data reading method of a nonvolatile memory device includes receiving an initial seed corresponding to a selected page of the nonvolatile memory device and relative location information of read-requested random data in the selected page. The method further includes generating a seed for randomizing the random data by subjecting the initial seed and the location information to a finite field arithmetic operation, and de-randomizing the random data based on a random sequence generated from the seed.

Abstract translation: 非易失性存储器件的随机数据读取方法包括：接收与所述非易失性存储器件的选定页面相对应的初始种子和所选页面中所读取的随机数据的相对位置信息。 该方法还包括通过对初始种子和位置信息进行有限域算术运算来产生用于随机化随机数据的种子，以及基于从种子生成的随机序列对随机数据进行去随机化。